現有一系列用高碼率，長碼長之校驗矩陣定義的低密度奇偶檢查碼。我們想觀察這些矩陣使用縱向式解碼的模擬結果，如使用軟體測試，想跑到發生錯誤地板(error floor)的資料點將耗費上萬天的模擬時間。為節省模擬時間，本論文將採用硬體的方式來測試，將縱向式解碼器用電路實現後，將其掛載到FPGA平台測試。但如採用傳統縱向式解碼器電路架構，其電路面積會過大，所占用的資源將超過FPGA板所提供的。為解決此問題，本論文採用了降低解碼器平行度的方式，在此使用新的排程法來達成目的，此排程法取名為折線排程，解碼器的面積將下降27%。此外，為加快FPGA驗證速度，本論文提出了預先載入(preload)的技術來減少解碼迭代次數以加快解碼器吞吐量。於高SNR的資料點，吞吐量25%至33%。

It will take a long time to obtain error-floor results of Low-Density Parity Check Codes using software simulation. To shorten the simulation time, this paper uses FPGA-based emulation to evaluate the error-floor performance. Shuffled LDPC decoder is implemented using FPGA. The conventional shuffled decoder architecture is very large so that the FPGA resource is not enough. We reduce parallelism of the decoder to solve this problem. This paper proposes a new schedule method to achieve this goal. Approximate 27% of the total area is reduced. In addition, we propose a new preloading technique to increase throughput of the decoder. This new technique can provide an increased throughput so that the shorter simulation times can be achieved.

[1] D. J. C. MacKay and R. M. Neal,Near Shannon limit performance of low density parity check codes,Electron. Lett., vol. 32, no. 18, pp.16451646, 1996.
[2] R. G. Gallager, Low-density parity-check codes,IRE Trans. Inf. Theory,vol. 8,no. 1, pp. 2128, 1962.
[3] IEEE Standard for Information technology Local and metropolitan area networks Specic requirements Part 11: Wireless LAN Medium Access Control(MAC)and Physical Layer (PHY) Specications Amendment 5: Enhancements for Higher Throughput.IEEE-SA, 2009.
[4] IEEE Standard for Air Interface for Broadband Wireless Access Systems.IEEESA, 2012.
[5] Unied high-speed wireline-based home networking transceivers - System architecture and physical layer specication. ITU-T, 2011.
[6] M. P. C. Fossorier, M. Mihaljevic, and H. Imai, "Reduced complexity iterative decoding of low-density parity check codes based on belief propagation," in IEEE Trans. Commun., vol. 47, no. 5, pp. 673680, May.1999.
[7] J.Zang,M.P.C FossorierShued Iterative DecodingIEEE Trans.Communication. Theory,vol. 53,no. 6,pp. 209-213, Feb. 2005.
[8] M. M. Mansour and N. R. Shanbhag, Turbo decoder architectures for low-density parity-check codes, in IEEE Global Telecommunications Conference,vol. 2, pp. 13831388, 2002.
[9] Tom Richardson "Error Floors of LDPC Codes," in proc. 41st Allerton Conf. on Communications, Control, and Computing, Allerton House,Monticello,IL ,Oct.2003.
[10] Ying-Chi Hou "Implementation of Flexible QC-LDPC codec on FPGA,"in NTHU Master Thesis, 2015.
[11] R. M. Tanner,A recursive approach to low-complexity codes, IEEE Trans. Inf. Theory,vol. IT-27, no. 5, pp.533-547, Sep. 1981.
[12] Z. Li, L. Chen, L. Zeng, S. Lin, and W. H. Fong, "Ecient encoding of quasi-cyclic low-density parity-check codes," in IEEE Trans. Commun,vol. 54, no. 1, pp. 7181, 2006.
[13] Hsueh-Chih Chou "A Low-Complexity LDPC Codec for NAND Flash Memory" in NTHU Master Thesis, 2013.
[14] Jyun-Kai Hu, A Reduced-Complexity Layered Decoder Architecture for High-Rate QC-LDPC Codes,in NTHU Master Thesis, 2013.
[15] Yeong-Luh Ueng,Chung-Jay Yang,Kuan-Chieh Wang and Chun-Jung Chen, "A Multimode Shued Iterative Decoder Architecture for High-Rate RS-LDPC Codes,"in Circuits and Systems I: Regular Papers, IEEE Transactions on Year:2010, vol:57, issue:10.
[16] Yeong-Luh Ueng, Bo-Jhang Yang, Chung-Jay Yang, Huang-Chang Lee and Jeng-Da Yang, "An Ecient Multi-Standard LDPC Decoder Design Using Hardware-Friendly Shued Decoding"in Circuits and Systems I:Regular Papers, IEEE Transactions on Year:2013, vol:60, issue:3.