研究生: |
郭銘彬 Min-Pin Kuo |
---|---|
論文名稱: |
深次微米缺陷之路徑延遲診斷技術 Diagnosing Deep SubMicron Defects For Path Delay Fault |
指導教授: |
劉靖家
Jing-Jia Liou |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2004 |
畢業學年度: | 92 |
語文別: | 英文 |
論文頁數: | 56 |
中文關鍵詞: | 延遲診斷 |
外文關鍵詞: | delay diagnosis |
相關次數: | 點閱:3 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
延遲診斷 (delay diagnosis) 的目的是為了找出最有可能造成延遲錯誤的地方,一個有效率的診斷軟體可以提供設計者一組比較少且需要先檢查的地方,藉以減少重新設計所花費的時間。
在這篇論文中我們已經發展出一種新的延遲診斷方法,首先我們利用多次的測試分別找到每條受測路徑的上限 (upper bound) 和下限時間 (lower bound),然後我們將路徑的延遲時間轉換成線性方程式,當我們解出電路中每個區段的延遲時間 (segment delay) 後,我們可以依據這個結果告訴設計者那些地方是最有可能有延遲錯誤的地方,從實驗的結果中可以看出我們所提出的方法之診斷正確性。
The goal of diagnosis method is to determine the suspected faulty node which is the most probable
cause of the observed failures. An efficient diagnosis tool can drastically reduce the redesign time
by providing the designers with a small set of possible faults to investigate. In this thesis, we have
proposed a method of delay fault diagnosis. We apply a testing methodology [1] to have two times
for every path. These two times, form a lower and upper bound respectively on the delay of path.
We translate the path bound to linear programming equations [2]. We can solve the equations and
use the result for diagnosing delay defect. Then, we simplify the linear programming equation
in advance to improve diagnosis. The experimental result shows the accuracy of our diagnosis
methodology.
1
[1] M. Sharma and J. H. Patel, “Bounding Circuit Delay by Testing a Very Small Subset of
Paths”, Proceedings of IEEE VLSI Test Symposium, pp. 333–341, Apr. 2000.
[2] Brian D. Bunday, Basic Linear Programming, Edward Arnold, London, 1984.
[3] A. Krstic and K.-T. Cheng, Delay Fault Testing for VLSI Circuits, Kluwer Academic Publishers,
Boston, MA, 1998.
[4] P. Girard, C. Landrault, and S. Pravossoudovitch, “A Novel Approach to Delay-Fault Diagnosis”,
Proceedings of Design Automation Conference, pp. 357–360, June 1992.
[5] J. G. Dastidar and N. A. Touba, “A systematic Approach for Diagnosing Multiple Delay
Faults”, Symposium on Defect and Fault Tolerance, pp. 211–216, Nov. 1998.
[6] J. G. Dastidar and N. A. Touba, “Adaptive Techniques for Improving Delay Fault Diagnosis”,
Proceedings of IEEE VLSI Test Symposium, pp. 168–172, Apr. 1999.
[7] Y.-C. Hsu and S. K. Gupta, “A New Path-Oriented Effect-Cause Methodology to Diagnose
Delay Failures”, Proceedings of IEEE International Test Conference, pp. 758–767, Oct.
1999.
[8] P. Pant and A. Chatterjee, “Efficient Diagnosis of Path Delay Faults in Digital Logic Circuits”,
Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 471–
475, Nov. 1999.
[9] P. Pant, Y.-C. Hsu, S. K. Gupta, and A. Chatterjee, “Path Delay Fault Diagnosis in Combinational
Circuits With Implicit Fault Enumeration”, Proceedings of IEEE/ACM International
Conference on Computer-Aided Design, pp. 1226–1335, Oct. 2001.
[10] K. T. Cheng and H. C. Chen, “Delay testing for nonrobust untestable circuits”, Proceedings
of IEEE International Test Conference, pp. 954–961, Apr. 1993.
[11] W. K. Lam, A. Saldanha, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “Delay fault
coverage and performance tradeoffs”, Proceedings of Design Automation Conference, pp.
446–452, June 1993.
[12] U. Sparmann, D. Luxenburger, K. T. Cheng, and SM. Reddy, “Fast identificationof robust
dependent path delay faults”, Proceedings of Design Automation Conference, pp. 119–125,
June 1995.
[13] K. T. Cheng and H. C. Chen, “Classification and identification of nonrobust untestable path
delay faults”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
pp. 845–853, Aug. 1996.
[14] S. Padmanaban and S. Tragoudas, “An Implicit Path-Delay Fault Diagnosis Methodology”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1399–
1408, Oct. 2003.
[15] R. C. Tekumalla, S. Venkataraman, and J. G. Dastidar, “On Diagnosing Path Delay Fault
in an At-Speed Environment”, Proceedings of IEEE VLSI Test Symposium, pp. 28–33, Apr.
2001.
[16] Peter Notebaert, “Linear programming solver”, http://groups.yahoo.com/group/lpsolve,
2003.
[17] J. J. Liou, K. T. Cheng, and D. A.Mukherjee, “Path Selection for Delay Testing of Deep Sub-
Micron Devices Using Statistical Performance Sensitivity Analysis”, Proceedings of IEEE
VLSI Test Symposium, pp. 97–104, Apr. 2000.