憑藉著先進發展的金屬氧化物半導體技術，全機體化的金屬氧化物半導體雷達在感測器的應用上扮演極重要的角色小至生活周遭應用大致國防防衛用途，這篇論文主要包含兩顆金屬氧化物半導體寬頻雷達，分別為金屬氧化物半導體直接取樣雷達及金屬氧化物半導體頻率調變連續波雷達。
第一個晶片呈現一個結合高精準度數位延遲轉換器的直接取樣寬頻脈衝雷達，並且支援量測待測物距離的重要參數-飛行測距，實現的直接取樣接收器可以藉由等效取樣技術進而在數位端重建接收波型。詳細的鍊路運算確保雷達的偵測範圍可以涵蓋全部偵測範圍，在實現的直接取樣接收器雷達技術中，其飛行測距精準度與範疇取決於數位延遲轉換器的效能。因此在這實現中我們導入高精準度的數位延遲器去提供雷達高精準度的偵測實現，當中游標尺概念被應用於該數位延遲轉換器，過去有許多游標尺架構的作品，並用於實現高精準度的延遲調整，然而有別於過去其他作品利用延遲線實現，該作品利用被相位鎖相器鎖定的震盪器提供精準的游標尺延遲，因此實現的數位延遲轉換器可以有著皮秒的延遲調整，且因為該延遲被鎖定的震盪器所定義，因此針對製程電源溫度的變異有著相當程度的免疫力。全積體化的雷達包含雷達射頻前端、高精準度數位延遲轉換器、類比訊號處理器和類比數位轉換器是利用65奈米互補式金屬氧化物半導體所實現，核心面積(不含輸入輸出焊墊)為$2mm^2$，消耗88.4毫瓦功率該接收器提供10GHz連續瞬時前端頻寬可以完整地擷取全部的散射反射波型，進而達到666GS/s的等效取樣頻率完整擷取接收訊號給後端的數位訊號處理做進一步的分析進而偵測距離資訊。
第二個晶片實現一個結合單天線介面全積體化頻率調變連續波雷達以支援量測待測物距離的重要參數-飛行測距，當中利用的循環器架構合併雙天線雷達系統呈現單天線介面輸出。所使用的循環器架構，有別於先前大部分文獻提出利用訊號相消技巧，其將發射端和接收端訊號直接在頻率上做分隔，再藉由若干濾波器去達到更好的阻隔性，頻率調變連續波訊號是藉由分數型頻率合成器所產生，該產生器可產生400MHz頻率調變範圍。此實現的架構更利於全積體化雷達系統的設計詳細的鍊路運算確保雷達的偵測範圍可以涵蓋全部偵測範圍，全積體化的雷達包含雷達射頻前端、頻率合成器、類比訊號處理器和類比數位轉換器是利用65奈米補式金屬氧化物半導體所實現，晶片為$1.9\time 2 mm^2$，功率消耗為147毫瓦該循換器前端可以在X頻段提供10.5dBm發射功率、超過1GHz的前端匹配效果、最佳16.8dB的雜訊參數(包含後端放大器)、最佳2dBm輸入增益壓縮一分貝點、7dBm三階輸入截止點和2dB插入損耗該雷達系統搭配後端快速傅立葉轉換為主的演算法可被運用來實現一維和二維的無線實測進行距離與定位的運用，量測證實可提供37cm的量測距離精準度在400MHz的頻率調變情況下。

With the advanced development in CMOS technology, fully-integrated CMOS radar has played a significant role in sensor application from our daily life to military security. This dissertation consists mainly of two CMOS broadband radars, namely a CMOS direct-sampling pulsed radar and a CMOS FMCW radar.
The first chip presents a direct-sampling pulsed radar with a high-resolution digital-to-time converter (DTC) for estimating time of flight (TOF), which is to identify the distance between a target and radar. The implemented direct-sampling radar can reconstruct the scanning waveforms in digital domain. The link budget of the radar transceivers is analyzed for the overall scanning range. The scanning range of the radar is dependent on the TOF. The range resolution of the pulsed TOF radar is determined by timing resolution of DTC. With the help of exquisite DTC, a high resolution radar can be achieved. The vernier concept has been adopted to achieve an accurate timing resolution design in the DTC. The vernier time steps are defined by the oscillating frequency of the phase-locked loops (PLL), and therefore the DTC with a high resolution in the order of picosecond and with high immunity to PVT variation was developed and demonstrated. The proposed radar including radar transceiver, high resolution digital-to-time convernter,analog signals preocessing, and analog-to-digial converter was fabricated using 65nm CMOS technology and occupies a chip area of 2 $mm^2$, consumes 88.4 mW of DC power. The receiver has a 10GHz instantaneous front-end bandwidth for capturing all scattering reflected waveforms and a 666GS/s equivalent sampling rate for recording all received signals for subsequent digital signal processing (DSP) analysis.
The second chip presents a highly integrated frequency-modulated continuous wave (FMCW) radar with single antenna interface for sensing target distance. In this work, a ciruclator structure is included for single antenna interface radar system. This circulator structure takes advantage of characteristics of orthogonality on frequency to separate the transmitted and received signals and then the isolation can be improved by using integrated filters to further suppress transmitter leakage. Compared to conventional ones, using signal cancellation for better signal isolation, this work can provide better isolation performance and simple chip implementation in FMCW radar. The frequency-modulated continuous wave which is implemented by fractional-N PLL with MASH 1-1-1 sigma delta modulation directed by digital ramp generator can have a better potential on fully integrated radar design. Besides, the system consideration concerning depth resolution, and link budget are under discussion for system assessment. The highly-integrated radar composed of radar transceiver, frequency synthesizer, analog signal processing, and analog-to-digital converter was fabricated using 65nm CMOS technology, occupies a chip area of $1.9\time 2mm^2$, and consumes 147 mW DC power under 1.2 V power supply. The implemented front-end circuit can provide output power of 10.5dBm with power efficiency of 32$\%$, over 1GHz impedance matching, insertion loss of 2 dB, best noise figure of 16.8dB (including the following amplifier), $P_{1dB}$ of 2 dBm, and IIP3 of 7 dBm. The implemented radar system in accompany with FFT-based algorithm can be proven to implement 1-dimension and 2-dimension wireless positioning and distance sensing. The wireless measurement proved it can provide 37 cm range resolution under 400 MHz frequency modulation range.

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