Timing Characterization Methodology for Low-Power Single-Port SRAM Compiler

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研究生：	陳彥佑 Chen, Yen-Yu
論文名稱：	Timing Characterization Methodology for Low-Power Single-Port SRAM Compiler 對低功率單埠靜態隨機存取記憶體產生器之時序特性方法
指導教授：	黃錫瑜 Huang, Shi-Yu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	48
中文關鍵詞：	靜態隨機存取記憶體產生器、時序特性方法
外文關鍵詞：	SRAM Compiler, Timing Characterization Methodology
相關次數：	點閱：4 下載：0
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Memory usually has been used in the ASIC design. The performance of memory always play role in the overall circuit. In this thesis, we propose an efficient extrapolation-based timing equation method for SRAM complier that generates SRAM macros. Our proposed method only needs to simulate a small number of memory configurations with relatively small sizes. The obtained results are then extrapolated to any other configurations. In order to obtain the SRAM macros, we develop the SRAM compiler. We also discuss the implementation of SRAM compiler in this thesis.

在專用積體電路中，記憶體廣泛的被使用。記憶體的效能經常在電路裡扮演相當重要角色。在這篇論文當中，針對靜態隨機存取記憶體產生器所產生的靜態隨機存取記憶體提出了一個快速的具有外插能力的存取時間和週期時間方程式模型的方法。我們的方法只需要針對少量的小型記憶體做時序的模擬。經由這些小型記憶體的資料，使用外插方法推得其它不同架構的記憶體。為了取得靜態隨機存取記憶體，我們發展自己的靜態隨機存取記憶體產生器，在論文中，我們也會談論如何實現靜態隨機存取記憶體產生器。
本文內容概述如下：
在第一章中，說明研究動機及目的，並針對提出的時間方程式方法做簡扼說明以及描述其優點。
在第二章中，將介紹相關靜態隨機存取記憶體的常見的內部電路架構，並比較其優缺點，說明為何挑選使用於靜態隨機存取記憶體產生器電路架構中。
在第三章中，會談到如何實現靜態隨機存取記憶體產生器，針對內部重要觀念及細節做說明。
在第四章中，提出時間方程式的發想，推導及描述提出的時間方程式方法以及完整的流程。
在第五章中，針對提出的時間方程式設計實驗驗證，展示我們的實驗結果，跟傳統方法做比較。
在第六章中，針對本文下了最後結論。

Abstract (English)    I
Abstract (Chinese)    II
Acknowledgement (Chinese)    III
Content    IV
List of Figures    VI
List of Tables    VIII
Chapter 1 Introduction    1
1.1    Motivation    1
1.2    Thesis Organization    3
Chapter 2 CMOS SRAM Circuitry    4
2.1    Theoretical Background of SRAM Circuitry    4
2.2    SRAM Bit Cell    6
2.3    Row Decoder    9
2.4    Column Decoder Circuitry    14
2.4.1    Predecoder with Pass Transistor    14
2.4.2    Tree Decoder Column Multiplexer    15
2.5    Write Circuitry and Precharge Circuitry    16
2.5.1    Write Circuitry    16
2.5.2    Precharge Circuitry    17
2.6    Sense Amplifier    19
2.6.1    Latch-type Sense Amplifier    19
2.6.2    Current-mirror Sense Amplifier    20
2.6.3    Automatic-power-down Sense Amplifier    20
2.7    Timing Controller    22
2.7.1    Delay-Chain and Replica Based SRAM    22
2.7.2    APD Based SRAM    23
Chapter 3 Implementation of SRAM Compiler    24
3.1    Background    24
3.2    Overall Flow of SRAM Compiler    27
3.2.1    Generation of Layout    28
3.2.2    Generation of SPICE Netlist    30
3.3    Critical Path Circuitry of SRAM    31
Chapter 4 Timing Characterization    32
4.1    Explanations    32
4.2    Timing Characterization Methodology    35
4.3    Overall Flow    36
Chapter 5 Experimental Results    37
5.1    Critical Path Circuit vs. Whole Circuit    37
5.2    Predicting Value vs. Actual Value    40
5.3    Comparison and Summary    43
Chapter 6 Conclusions    44
Bibliography    45

                                

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