適用於2.56/3.2Gbps SERDES的雙模低抖動LC-VCO鎖相迴路

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研究生：	陳煥達 Huan-Ta Chen
論文名稱：	適用於2.56/3.2Gbps SERDES的雙模低抖動LC-VCO鎖相迴路 A Dual Mode Phase Locked Loops with low jitter LC-VCO for 2.56/3.2 Gbps SERDES
指導教授：	吳仁銘 Jen-Ming Wu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 通訊工程研究所 Communications Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	58
中文關鍵詞：	鎖相迴路、雙模、平衡直流電壓、抖動、峰對峰值抖動、射頻式互補式金氧半電晶體、接地式共平面波導
外文關鍵詞：	PLL, dual mode, dc-balance, jitter, peak to peak jitter, RFCMOS, GCPW
相關次數：	點閱：3 下載：0
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　　在當今的電路設計中，PLL “鎖相迴路”扮演一個關鍵的腳色，它可以從一個低速的週期時脈信號中得到一個輸出為高速的週期時脈信號。鎖相迴路有許多應用的層面，像是時脈與資料回復電路、延遲鎖相迴路、時脈合成與同步電路。在本篇論文，我們提出一個工作在雙模的鎖相迴路，這個電路工作於平衡直流電壓資料或是8位元以及10位元的錯誤偵測資料，在一個時域的正交分頻多工系統來降低峰值均值比。基於此架構，鎖相迴路的抖動的表現是越來越重要，像是在商業的系統架構需要較高速的資料傳輸。這一篇論文提出一個建立在鎖相迴路的完整流程圖。此架構建立了，相位雜訊在頻域的LC電壓控制震盪器，和抖動在時域的雙模鎖相迴路。此外，LC電壓控制震盪器被要求建立在非常低的相位雜訊以及能夠工作在雙模的速度下。因此，本電路採用許多創新的方式來降低抖動情況的發生，像是接地式共平面波導、射頻式互補式金氧半電晶體或是使用佈局設計的方式來有效的降低雜訊的影響。
　　這個鎖相迴路被設計以及製造在0.18微米台積電互補式金氧半電晶體混合訊號製程。此晶片的面積為長度1.2微米及寬度1.2微米。電壓控制震盪器操作的頻率在1280和1600百萬赫茲。功率消耗在34微瓦，提供的電壓是1.8伏特。系統工作的效能在峰對峰值的抖動是2.3 皮秒在1280百萬赫茲和2.5皮秒在1600百萬赫茲。

In many circuits, PLL “Phase Locked Loops” plays an important role in an output high speed clock to follow the slow input clock. Examples of application that uses PLL include clock and data recovery, delay locked loops, clock synthesis, and synchronization. In this thesis, we propose a dual mode PLL, which functions as sampling a DC-balanced or error detection 8B/10B data in the time domain of OFDM system to reduce PAPR. Based on the architecture, the jitter performance of PLL is getting more and more important, as communication system request higher data rate. The thesis proposes the complete flow chart which establishes the PLL block. It estimates LC-VCO phase noise in frequency domain and Dual Mode PLL jitters in time domain. Moreover, the proposed LC-VCO has very low phase noise and can be used to work at dual speed.
The PLL have been designed and fabricated in a 0.18um TSMC CMOS Mixed Signal technology .The chip area is 1.2mm * 1.2mm. The VCO operation frequency is 1280MHz and 1600MHz. The power consumption is 34mW and supply voltage is 1.8V. The performance of peak to peak jitter is 2.3ps at 1.28GHz and 2.5ps at 1.6GHz.

Introduction                                                    1
1    Load-balanced Birkhoff-von Neumann Switch . . . . . . . . . . . . . . . . . . 1
2    A 4 × 4 Load-Balanced Switch Fabric . . . . . . . . . . . . . . . . . . . . . . .. . .2
3    A Dual Mode PLL work at 2.56/3.2 Gbps . . . . . . . . . . . . . . . . . . . . . . .4

PLL Design Theory                                              7
1    PLL design concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2    System Linear Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3    PLL Behavior Model Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
         2.3.1   Phase Frequency Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2   Charge Pump & Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3   Voltage Control Oscillator & Frequency Divider . . . . . . . . . 17
4   PLL & design system parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5   How to get loop parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PLL Circuit Architecture                                         23
1   Phase-Locked Loop Design Concept . . . . . . . . . . . . . . . . . . . . . . . . . .23
2   Phase Frequency Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3   Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4   Voltage Control Oscillator and Divider . . . . . . . . . . . . . . . . . . . . . . . . .29
4.1   LC-VCO Output Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.2   NMOS Varactor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . ..31
4.3   Cross Coupled Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..33
4.4   VCO Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34


4.5   VCO Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.6   TSPC Divider  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

PLL Layout and Post-Simulation                                    42
1   Layout Skill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
1.1   GCPW and Transmission Line . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
1.2   RF-CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
1.3   Layout Floor Plans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.4   Simulation with Parasitic Capacitor and Resistor  . . . . . . . . . . . . .46
2   Prediction Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.1   This Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
1.2   Work 4x4 TDM Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Conclusion and Future Work                                        56

  Bibliography                                                     57

                                

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