為了滿足ITRS元件持續縮小化的要求，一般廣泛的認為高介電係數材料將取代原本的二氧化矽成為金氧半元件閘極介電層來改善漏電流的問題，然而在材料替換的過程中，許多問題產生，如電荷捕獲(charge trapping)、臨界電壓(threshold voltage)飄移、載子遷移率下降(mobility degradation)等，因此應用在高介電係數閘極介電層電晶體的界面陷阱(interface traps)及氧化層陷阱(oxide traps)可靠度分析因應而生。
論文中第一部份介紹電荷汲引技術量測方法。利用電荷汲引量測high-κ介電層電晶體的界面陷阱密度與邊緣陷阱密度。描繪出陷阱空間中的分佈以及在矽能隙中能量的分佈情形。
接著探討高介電係數介電層的特性，比較不同厚度、材料，藉著電荷汲引量測技術量測，觀察high-κ介電層的好壞，以及CVS後界面陷阱與邊緣陷阱的變化。發現NMOS中摻雜La可有效提高可靠度。
最後於高溫下施加應力，作BTI可靠度的量測，可發現PBTI於NMOS主要產生的是邊緣陷阱，而NBTI於PMOS則產生多增加在界面陷阱。進而改變應力之極性，於元件可靠度做更深入觀察，發現NPMOS皆隨著溫度升高而有修補的情形出現，使得界面陷阱的產生趨緩。

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