With the growing demand for portable and handheld products, system-on-chip (SoC) design with power management mechanism has become a popular trend to extend the battery life. Power management system is incorporated in our chip such that the overall power efficiency can be maximized. Low-dropout (LDO) voltage regulator which is regarded as an essential part in power management system has good transient response and ripple rejection capability. However, it suffers from low power efficiency problem and hard for SoC integration.

A modified nested miller compensation scheme for LDO is proposed to solve the above problems in this thesis. The proposed architecture utilizes pole splitting principles such that system stability is guaranteed. Moreover, power efficiency is greatly improved by operating power transistor in triode region while consuming low quiescent current. The settling time is not affected by low current consumption. Instead, it is improved by additional feedback loop for directly sensing the output voltage variations. The proposed 1 V LDO regulator with a supply voltage of 1.05 V was simulated by HSPICE and fabricated in TSMC 0.18 μm CMOS technology with an area of 997 x 908 μm2. The whole chip consumes only 32 μA of ground current with an ultra-low-dropout voltage of 50 mV.

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