電荷幫浦是一種簡單的DC-DC電壓轉換電路，它利用電容儲存電荷能量，并利用週期電壓控制轉換開關的開閉，來使得電荷不斷的從上一級累積到下一級，從而達到升高電壓的效果。由於其簡單的架構以及較高的電壓轉換效率，已被廣泛應用在了電壓轉換器，穩壓器，電源管理電路及鎖相環電路中。建立電路模型分析電路對於電路的設計與最優化有很大的幫助，目前所使用的電荷幫浦電路皆為基本型的Dickson電荷幫浦電路的改良，而現有的電荷幫浦電路建模分析亦都基於Dickson電荷幫浦電路的架構。此篇論文將在Dickson電荷幫浦的電路建模上做一些討論與研究，并針對現有的電路分析模型在預測電路特性上的一些缺陷（例如無法分析晶體管寬度對於電路穩態輸出電壓的影響），提出了一種新的帶有等效閾值電壓參數的Dickson電荷幫浦的電路模型，此模型可以較準確的分析Dickson電荷幫浦的穩態輸出電壓與幾個影響參數之間的關係。

由於目前的電荷幫浦電路的儲電電容（Charging Capacitor）主要是采用線性電容，這使得電荷幫浦電路存在所佔電路面積過大的問題，這在崇尚最優化設計的IC設計領域是非常不利的。由此本論文提出了使用變容二極管（Varactor）取代線性電容作為儲電電容的設計，并利用本文提出的等效閾值電壓Dickson電荷幫浦電路模型對其做了電路面積最小化的最優化設計，使得最優化設計後的電路相對使用傳統線性電容且未做最優化設計的Dickson電荷幫浦電路的面積有很大的優勢。

此篇論文的模擬條件皆基於台積電0.18um製程，其目標穩態輸出電壓為1.5V，穩態輸出電流為10uA。

Charge pump is a kind of DC-DC converter circuit which uses capacitors as energy store elements to create a higher output steady voltage. It’s widely used in voltage converter, power management system and phase lock loop because of its simple circuit structure and high power efficiency. Building the circuit model to do analysis work is helpful for circuit design and optimization. Dickson charge pump circuit is the fundamental and most widely used charge pump circuit. The conventional analytical model based on the Dickson charge pump is studied in this thesis. An improved Dickson charge pump model with an effective Vth parameter is derived in response to the drawbacks of the conventional model (as can’t be used to analysis the effect of MOS width on the circuit performance). The improved model can predict the steady-state output voltage more accurate.

As linear capacitor is used as the charging capacitor in the charge pump circuit, the circuit area problem can’t be ignored. Larger circuit area leads to larger costs, so circuit area optimization work should be done on the design of charge pump circuit. In this thesis, to decrease the circuit area, a new design using varactor as the charging capacitor to replace of linear capacitor is derived. An improved area minimization work based on the effective threshold voltage Dickson charge pump model and varator charging capacitor is done on the Dickson charge pump circuit. Circuit which has been done by this area optimized work will have great area advantage compared to the conventional Dickson charge pump circuit which hasn’t been area optimized.

In this thesis, all simulations are based on TSMC 0.18um CMOS model. The clock has an amplitude of -1.5V to 1.5V, of which frequency is 100 (KHz) and the duty cycle is 50%. The objective steady-state output voltage is 1.5 (V) and output current is 1 0(uA).

Reference
[1]. Cockcroft, J.D. and E.T. Walton, “Production of high velocity positive ions,” Proceedings of the Royal Society, A, Vol. 136, pp. 619–630, 1932.
[2]. Dickson, J. “On-chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique.” IEEE Journal ofSolid-State Circuits, Vol. 11, No. 6, pp. 374–378, June 1976.
[3]. Louie Pylarinos, “Charge Pumps: An Overview,” Department of Electrical and Computer Engineering, University of Toronto.
[4]. Giuseppe Di Cataldo and Gaetano Palumbo, “Double and triple charge pump for power IC: ideal dynamical models to an optimised design,” IEE Proceedings G, Circuit Devices & Systems, Feb. 1993.
[5]. Tanzawa T. “Dickson charge pump circuit design with parasitic resistance in power lines”, Circuits and Systems, ISCAS 2009. IEEE International Symposium on. IEEE, pp. 1763-1766. Sep. 2009.
[6]. J. S. Witters, G. Groeseneken, and H. E. Maes, “Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits,” IEEE J. Solid-State Circuits, vol. 24, pp. 1372–1380, Oct. 1989.
[7]. Giuseppe Di Cataldo and Gaetano Palumbo, “Dynamic analysis of 3 stage Dickson voltage multiplier for an optimized design,” Proceedings 7th Mediterranean Electrotechnical Conference, Apr. 1994.
[8]. Toru Tanzawa and Tomoharu Tanaka, “A Dynamic Analysis of the Dickson Charge Pump Circuit,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 8, Aug. 1997.
[9]. Ming Zhang and Nicolas Laser, “Dynamic analysis of Dickson charge pump circuits with a resistive load,” Proceedings of the 2003 10th IEEE International Conferenceon Electronics, Circuits and Systems, Vol. 2, 2003.
[10]. Chih-Huei Hu and Lon-Kou Chang, “Analysis and Modeling of On-Chip Charge Pump Designs Based on Pumping Gain Increase Circuits With a Resistive Load,” IEEE Transctions on Power Electonics, Vol. 23, No. 4, July. 2008.
[11]. Gaetano Palumbo, Domenico Pappalardo, and Maurizio Gaibotti, “Charge-Pump Circuits: Power-Consumption Optimization,” IEEE Transactions on circuits and systems I: Fundamental Theory and Applications, Vol. 49, No. 11, Nov. 2002.
[12]. Zhang M, Llaser N. “Optimization design of the Dickson charge pump circuit with a resistive load”, Circuits and Systems, ISCAS'04. Proceedings of the 2004 International Symposium on. IEEE, Vol. 5. May. 2004
[13]. C. Wang and J. Wu, “Efficiency improvement in charge-pump circuits,” IEEE J. Solid-State Circuits, vol. 32, pp. 852–860, June 1997.
[14]. Maget J, Tiebout M, Kraus R. “MOS Varactors With n-and p-Type Gates and Their Influence on an LC-VCO in Digital CMOS”. IEEE Journal of Solid-State Circuits, Vol. 38, No. 7, pp. 1139-1147. Jun. 2003.
[15]. Chan Y J, Huang C F, Wu C C, et al. “Performance consideration of MOS and junction diodes for varactor application”. IEEE Transactions on Electron Devices, Vol. 54, No. 9, pp. 2570-2573. Sep. 2007.
[16]. Molnar K, Rappitsch G, Huszka Z, et al. “MOS varactor modeling with a subcircuit utilizing the BSIM3v3 model”. IEEE Transactions on Electron Devices, Vol. 49, No. 7, pp. 1206-1211, Jun. 2002.
[17]. Gildenblat G, Zhu Z, Wu W. “Analytical expression for the bias and frequency-dependent capacitance of MOS varactors”. IEEE Transactions on Electron Devices, Vol. 54, No. 11, pp. 3107-3108, Nov. 2007
[18]. Andreani P, Mattisson S. “On the use of MOS varactors in RF VCOs”. IEEE Journal of Solid-State Circuits, Vol. 35, No. 6, pp. 905-910, Jul. 2000.