隨著製程的進步，全域繞線變得越來越困難。在這篇論文，我們提出一個考慮細部繞線器可繞線性的全域繞線器。在 ICCAD’19 [1] 全域繞線器競賽中，有別於 ISPD’08 [2] 全域繞線器競賽，為了考慮細部繞線的可繞線性，此競賽要求全域繞線器產生矩形的繞線指引，而不是單一的路徑，此外，繞線器的輸入必須為 LEF/DEF 的格式。因此，我們提出一個名為蓋瑞的全域繞線架構，此架構沿用 NTHU-Route 2.0 [3] 之二維全域繞線器，並採用修改版的層分配演算法 COALA [4]。為了提升細部繞線可繞線性，我們參考 SPRoute 2.0 [5] 之軟容量保留方法，並且修改 RUDY [6] 的算法，考量層之繞線方向以及引腳的層之資訊。從實驗結果得知，比起目前已知最好的方法之一 CUGR [7]，我們的方法能在每筆測資都取得更好的分數，平均而言總分能得到 2% 的進步，DRC 的總分能取得 30% 的進步，且又能以41% 之時間完成所有測資。相較於目前另一已知最新方法 SPRoute 2.0，我們能在總分得到 2% 的進步，DRC 的總分也能取得 17% 的進步。

Global routing becomes more and more difficult along with the shrinkage of the technology node. In the ISPD’08 contest [2], a global router is required to generate a tree for each net, and the resources are given and known beforehand. However, in the ICCAD’19 contest [1], a global router needs to generate a routing guide rather than a tree for each net, and the input is in the LEF/DEF format, which means the router should evaluate the resources by itself. Moreover, the quality of the global router is evaluated by the DRC violations generated from a detailed router, in addition to the routed wirelength and the amount of vias. In this thesis, we propose a global routing framework named GARY which targets the ICCAD’19 benchmarks. GARY first compresses a 3D routing space into a 2D one and then utilizes the 2D global router from NTHU-Route 2.0 [3] plus a layer assignment algorithm modified from COALA [4] to get a routing result. Furthermore, capacity reduction methods based on SPRoute 2.0 [5] are also adopted in our framework, which give more accurate routing demand estimation under the consideration of the preferred routing direction of each routing layer and the layer of each pin. The experimental results show that the quality of GARY is better in all testcases than the state-of-the-art global router CUGR [7]; on average, it achieves 2% better total score and 30% better total DRC score, while its runtime is 59% shorter than CUGR run in a single thread. Compared to another router, SPRoute2.0 [5], GARY also won with 2% better total score and 17% better total DRC score.

[1] S. Dolgov, A. Volkov, L. Wang, and B. Xu, “2019 cad contest: Lef/def based global routing,” in Proceedings of International Conference on Computer-Aided Design (ICCAD), pp. 1–4, 2019.
[2] G.-J. Nam, C. Sze, and M. Yildiz, “The ispd global routing benchmark suite,” in Proceedings of International Symposium on Physical Design, pp. 156–159, 2008.
[3] Y.-J. Chang, Y.-T. Lee, and T.-C. Wang, “Nthu-route 2.0: A fast and stable global router,” in Proceedings of International Conference on Computer-Aided Design, pp. 338–343, 2008.
[4] Y.-J. Jiang and S.-Y. Fang, “Coala: Concurrently assigning wire segments to layers for 2d global routing,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022.
[5] J. He, U. Agarwal, Y. Yang, R. Manohar, and K. Pingali, “Sproute 2.0: A detailedroutability-driven deterministic parallel global router with soft capacity,” in Proceedings of Asia and South Pacific Design Automation Conference, pp. 586–591, 2022.
[6] P. Spindler and F. M. Johannes, “Fast and accurate routing demand estimation for efficient routability-driven placement,” in Proceedings of Design, Automation Test in Europe Conference, 2007.
[7] J. Liu, C.-W. Pui, F. Wang, and E. F. Young, “Cugr: Detailed-routability-driven 3d global routing with probabilistic resource model,” in Proceedings of Design Automation Conference, 2020.
[8] W.-H. Liu, W.-C. Kao, Y.-L. Li, and K.-Y. Chao, “Nctu-gr 2.0: Multithreaded collisionaware global routing with bounded-length maze routing,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 5, pp. 709–722, 2013.
[9] Y. Xu, Y. Zhang, and C. Chu, “Fastroute 4.0: Global router with efficient via minimization,” in Proceedings of Asia and South Pacific Design Automation Conference, pp. 576–581, 2009.
[10] H. Li, G. Chen, B. Jiang, J. Chen, and E. F. Young, “Dr. cu 2.0: A scalable detailed routing framework with correct-by-construction design rule satisfaction,” in Proceedings of International Conference on Computer-Aided Design, 2019.
[11] Innovus Implementation System. https://www.cadence.com/.
[12] ICCAD Problem C. http://iccad-contest.org/2019/Problem_C/2019ICCAD_ProblemC_V6_total.pdf/.
[13] C. Chu and Y.-C. Wong, “Flute: Fast lookup table based rectilinear steiner minimal tree algorithm for vlsi design,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1, pp. 70–83, 2007.
[14] T.-H. Lee and T.-C. Wang, “Congestion-constrained layer assignment for via minimization in global routing,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 9, pp. 1643–1656, 2008.
[15] Boost C++ Libraries. http://www.boost.org/.