簡易檢索 / 詳目顯示

研究生: 劉晉亨
Liu, Chin-Heng
論文名稱: 利用冗餘移除與全面性權重分配的方法來識別臨界值函數的研究
Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments
指導教授: 王俊堯
Wang, Chun-Yao
口試委員: 黃俊達
Huang, Juinn-Dar
溫宏斌
Wen, Hung-Pin
學位類別: 碩士
Master
系所名稱:
論文出版年: 2018
畢業學年度: 106
語文別: 英文
論文頁數: 31
中文關鍵詞: 臨界值邏輯閘臨界值函數辨別冗餘移除權重分配
外文關鍵詞: Linear threshold logic gate, Threshold function identification, Redundancy removal, Weight assignments
相關次數: 點閱:2下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 在臨界值邏輯的理論中,臨界值函數的辨別方法是一個基本卻很重要的工作,它可以決定一個布林函數是否可以被單一臨界值邏輯閘呈現。在此理論中,藉由建立非冗餘的不等式系統與全面性權重分配,我們提出一個更有效率與效能的臨界值邏輯函數辨別演算法。這是第一個可以辨別所有8輸入臨界值函數的非整數線性規劃的演算法。從實驗結果中,我們顯示出提倡的方法比所有現存的非整數線性規劃方法更加有效,以及提倡的方法產生出的臨界值邏輯閘有將近100%的機率會是最佳的。對於9到15輸入臨界值函數,提倡的方法也可以在合理的執行時間內,辨別出所有由隨機產生的100,000個臨界值函數。


    The identification of threshold function, which determines whether a Boolean function can be represented by an LTG or not, is a fundamental but important task in the theories of threshold logic. In this thesis, we propose a more efficient and effective algorithm of threshold function identification by constructing the system of irredundant inequalities and adjusting the weight assignment comprehensively. This is the first non-ILP-based approach that is able to identify all the 8-input threshold functions. The experimental results demonstrated that the proposed approach is more effective than all the existing non-ILP-based approaches and the LTGs obtained by the proposed approach are optimal for near 100\% cases. For threshold functions with 9 to 15 inputs, the proposed approach can identify 100,000 randomly generated threshold functions as well in a reasonable CPU time.

    中文摘要 i Abstract ii Acknowledgement iii Contents iv List of Tables vi List of Figures vii 1 Introduction 1 2 Preliminaries 5 2.1 Linear Threshold Gate . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Threshold Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Irredundant Sum-of-Products . . . . . . . . . . . . . . . . . . . . . . 6 2.4 Modified Chow’s Parameter . . . . . . . . . . . . . . . . . . . . . . . 6 3 Algorithm 8 3.1 The Review of the State-of-the-art . . . . . . . . . . . . . . . . . . . 8 3.2 Generation of the System of Irredundant Inequalities . . . . . . . . . 11 3.2.1 Redundant Weighted Summation Removal . . . . . . . . . . . 12 3.2.2 Redundant Inequality Removal . . . . . . . . . . . . . . . . . 12 3.3 Weight Assignment Procedure . . . . . . . . . . . . . . . . . . . . . . 14 3.3.1 The Review of the State-of-the-art [15] . . . . . . . . . . . . . 14 3.3.2 Proposed Weight Assignment Method . . . . . . . . . . . . . . 17 3.4 Threshold Value Computation . . . . . . . . . . . . . . . . . . . . . . 21 3.5 Overall Flowchart of TF Identification Algorithm . . . . . . . . . . . 21 4 Experimental Results 23 4.1 Effectiveness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 Optimality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 Applicability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 Conclusion 28

    [1] C. Augustine, G. Panagopoulos, B. Behin-Aein, S. Srinivasan, A. Sarkar, and
    K. Roy, “Low-power Functionality Enhanced Computation Architecture Using
    Spin-based Devices,” in Proc. Int. Symp. on Nanoscale Architecture, 2011, pp.
    129-136.
    [2] M. J. Avedillo, J. M. Quintana, H. Pettenghi, P. M. Kelly, and C. J. Thompson,
    “Multi-Threshold Threshold Logic Circuit Design using Resonant Tunnelling
    Devices,” Electron. Lett., pp. 1502-1504, vol. 39, 2003.
    [3] I. A. Basheerg, and M. Hajmeer, “Artificial Neural Networks: Fundamentals,
    Computing, Design, and Application,” Journal of Microbiological Methods, pp.
    3-31, 2000.
    [4] V. Beiu, J. M. Quintana, and M. J. Avedillo, “VLSI Implementations of Threshold
    Logic-A Comprehensive Survey,” IEEE Trans. on Neural Networks, vol. 14,
    pp. 1217-1243, 2003.
    [5] Y.-C. Chen, R. Wang, and Y.-P. Chang, “Fast Synthesis of Threshold Logic
    Networks with Optimization,” in Proc. Asia and South Pacific Design Automation
    Conf., 2016, pp. 486-491.
    [6] D. Goldharber-Gordon, M. S. Montemerlo, J. C. Love, G. J. Opiteck, and J.
    C. Ellenbogen, “Overview of Nanoelectronic Devices,” in Proc. IEEE, 1997, pp.
    521-540.
    [7] T. Gowda, S. Vrudhula and G. Konjevod, “A Non-ILP based Threshold Logic
    Synthesis Methodology,” in Proc. Int’l Workshop on Logic & Synthesis, 2007.
    [8] T. Gowda, S. Vrudhula, N. Kulkarni, and K. Berezowski, “Identification of
    Threshold Functions and Synthesis of Threshold Networks,” IEEE Trans. on
    Computer-Aided Designs, vol. 30, no. 5, pp. 665-677, 2011.
    [9] G. B. Huang, Q. Y. Zhu, K. Z. Mao, C. K. Siew, P. Saratchandran, and N. Sundararajan,
    “Can Threshold Networks Be Trained Directly?,” IEEE Trans. Circuits
    Syst. II, Exp. Briefs, 53(3), pp. 187-191, 2006.
    [10] P.-Y. Kuo, C.-Y. Wang, and C.-Y. Huang, “On Rewiring and Simplification for
    Canonicity in Threshold Logic Circuits,” in Proc. ICCAD, pp. 396-403, 2011.
    [11] Y.-A. Lai, C.-C. Lin, C.-C. Wu, Y.-C. Chen, and C.-Y. Wang, “Efficient Synthesis
    of Approximate Threshold Logic Circuits with an Error Rate Guarantee,”
    in Proc. DATE, 2018.
    [12] C.-C. Lin, C.-Y. Wang, Y.-C. Chen, and C.-Y. Huang, “Rewiring for Threshold
    Logic Circuit Minimization,” in Proc. DATE, 2014, pp. 1-6.
    [13] C.-C. Lin, C.-W. Huang, C.-Y. Wang, and Y.-C. Chen, “In&Out: Restructuring
    for Threshold Logic Network Optimization,” in Proc. ISQED, 2017, pp. 413-
    418.
    [14] S. Muroga,“Threshold Logic and its Applications,” New York, NY: John Wiley,
    1971.
    [15] A. Neutzling, M. G. A. Martins, V. Callegaro, and A. I Reis, R. P. Ribas,
    “A Simple and Effective Heuristic Method for Threshold Logic Identification,”
    IEEE Trans. on Computer-Aided Design, vol. PP, Issue. 99, 2017.
    [16] M. Perkowski, and A. Mishchenko, “Logic Synthesis for Regular Fabric Realized
    in Quantum dot Cellular Automata,” Journal of Multiple-Valued Logic and Soft
    Comput., pp. 768-773, 2004.
    [17] V. Saripalli, L. Liu, S. Datta, and V. Narayanan, “Energy-delay Performance
    of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated
    Logic Circuits,” Journal of Low Power Electronics, vol. 6, pp. 415-428, 2010.
    [18] C.-K. Tsai, C.-Y. Wang, C.-Y. Huang, and Y.-C. Chen, “Sensitization Criterion
    for Threshold Logic Circuits and its Application,” in Proc. ICCAD, pp. 226-233,
    Nov. 2013.
    [19] J. Schlachter, V.Camus, and C. Enz, “Near/Sub-Threshold Circuits and Approximate
    Computing: The Perfect Combination for Ultra-Low-Power Systems,”
    in Proc. ISVLSI, 2015, pp. 476-480.
    [20] R. O. Winder, “Single Stage Threshold Logic,” Switching Circuit Theory and
    Logical Design, pp. 321-332, 1961.
    [21] R. O. Winder, “Threshold Logic,” Ph.D. dissertation, Princeton University,
    Princeton, NJ, 1962.
    [22] R. O. Winder, “Enumeration of Seven-Argument Threshold Functions,” IEEE
    Trans. on Electronic Computers, pp. 315-325, 1965.
    [23] R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, “Threshold Network Synthesis
    and Optimization and Its Application to Nanotechnologies,” IEEE Trans.
    Computer-Aided Design, vol. 24, no. 1, pp.107-118, 2005.

    QR CODE