簡易檢索 / 詳目顯示

回結果列表
研究生： 吳敏瑞
Wu, Min-Rui
論文名稱： 一個12位元每秒取樣四十萬次之列並行混合式類比數位轉換器使用異步自適應電荷注入單元和單斜坡轉換
A 12-bits 400KS/s Column-Parallel Hybrid Analog-to-Digital Converter Using Asynchronous Self-Adaptive Charge-Injection Cell and Single-Slope Conversion
指導教授： 謝志成
Hsieh, Chih-Cheng
口試委員: 陳信樹
Chen, Hsin-Shu
洪浩喬
Hong, Hao-Chiao
張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2022
畢業學年度： 110
語文別： 英文
論文頁數： 74
中文關鍵詞： 類比數位轉換器 、列並行類比數位轉換器 、電荷注入 、混合式類比數位轉換器
外文關鍵詞： ADC, Column-parallel, Charge-injection, Hybrid ADC
相關次數： 點閱：2  下載：0 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 本文提出一個12位元每秒取樣四十萬次之列並行混合式類比數位轉換器(analog-to-digital converter, ADC) 使用異步自適應電荷注入單元(asynchronous self-adaptive charge-injection cell)和單斜坡(single-slope)轉換。
    作為影像感測器之讀出電路，列並行式類比數位轉換器需要在較小的間距寬度達到較高的取樣頻率，因此本論文提出一種可重複使用之電荷注入電路和單斜坡電路組成之混合式架構，以此來降低轉換時間。並提出自適應電荷注入方式，提供了異步操作，使其僅依靠電容和電壓比例，降低由製成、電壓、溫度(Process-Voltage-Temperature, PVT)導致之列與列之間的不匹配問題。此外，電荷注入利用取樣訊號之電荷，而不須額外提供切換能量，因此可以有效降低功耗。
    為驗證此架構，本電路之晶片採用40奈米1P9M互補式金氧半導體製程製作，核心電路面積為1250×800〖μm〗^2，且列並行式類比數位轉換器陣列之間距寬度為4μm。在1.5伏特電源電壓及400千赫茲取樣頻率操作下，本晶片可以達到SNDR為58.4dB，對應之ENOB為9.4-bit，其功耗為25.6μW，換算之能源效率指標(Walden figure-of merit, FoMw)為62.5fJ/conversion-step。

    A 12-bits 400KS/s column-parallel hybrid analog-to-digital converter (ADC) using asynchronous self-adaptive (SA) charge-injection cell (ci-cell) and single-slope (SS) conversion.
    As the readout circuit of the CMOS image sensor (CIS), the column-parallel ADC is required to achieve a high sampling frequency within a small pitch width. Thus, the proposed hybrid ADC uses a reusable ci-cell and a single ramp circuit to reduce conversion time. The proposed self-adaptive charge injection method provides asynchronous operation to reduce the column-to-column mismatch created by process-voltage-temperature (PVT) variation. In addition, the charge injection utilizes the charge of the sampled signal without additional switching energy to achieve energy efficiency.
    The prototype was fabricated in 40nm 1P9M CMOS technology with a core area of 1250×8〖μm〗^2, and the pitch width of column-parallel ADCs is 4μm. At 1.5V supply voltage and 400KS/s sampling rate, the ADC achieves SNDR 58.4dB and corresponding ENOB 9.4-bit with consumes 25.6μW power, resulting FoMw 62.5fJ/conversion-step.

    Abstract iii Content iv List of Figures viii List of Tables xi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Architecture Selection 1 1.3 Target Specifications 3 Chapter 2 Background of ADC 5 2.1 Performance Metrics of ADC 5 2.1.1 Nyquist Theorem 5 2.1.2 Resolution 5 2.1.3 Quantization Error 6 2.1.4 Offset and Gain Error 8 2.1.5 Differential Nonlinearity 9 2.1.6 Integral Nonlinearity 10 2.1.7 Signal-to-Noise Ratio 10 2.1.8 Signal-to-Quantization-Noise Ratio 10 2.1.9 Signal-to-Noise and Distortion Ratio 11 2.1.10 Spurious-Free Dynamic Range 11 2.1.11 Effective Number of Bits 12 2.1.12 Figure-of Merit 12 2.2 Basic SS ADC 12 2.2.1 Introduction of SS ADC 12 2.2.2 Sample and Hold Circuit 13 2.2.3 Charge Injection Effect 15 2.2.4 Clock Feedthrough 16 2.2.5 kT/C Noise 17 2.2.6 Comparator 18 2.2.7 Input Refferred Offset 19 2.2.8 Counter 20 2.2.9 Double Data Rate 20 Chapter 3 Column ADC Overview 22 3.1 Column-Shared ADC 22 3.1.1 SAR ADC [8] 22 3.1.2 Multi-Stage Cyclic-SAR ADC [9] 23 3.1.3 Analysis of Column-Shared ADC 24 3.2 Column-Parallel ADC 24 3.2.1 Dual-Slope (or two-step) ADC [10] 25 3.2.2 Time-Stretched SS ADC [2] 26 3.2.3 Time-to-Digital Converter SS ADC [3] 28 3.2.4 Charge-Injection SAR ADC 29 3.2.5 Summary 31 Chapter 4 Circuit Design Considerations 32 4.1 Hybrid Architecture 32 4.2 Sample and Hold Circuit 33 4.3 Dual-Mode Comparator 34 4.4 Global Gray Code Counter 35 4.5 Global Ramp Generator 36 4.6 Charge-Injection 37 Chapter 5 Circuit Implementation of Proposed SA CI ADC with SS 38 5.1 Architecture of Proposed SA CI ADC with SS 38 5.2 Architecture and Operation of Proposed Self-Adaptive Charge-Injection 41 5.2.1 Architecture and Operation of SA CI 41 5.2.2 Linearity Range 43 5.2.3 Noise 45 5.3 Single-Slope Conversion 46 5.4 Mixed Matching for Hybrid Architecture 46 5.5 Sample and Hold Circuit 48 5.6 Dual-Mode Comparator 50 5.7 Global Gray Code Counter 51 5.8 Global Ramp Generator 54 5.9 Design of Capacitor Array 57 5.10 Summary 57 Chapter 6 Measurement Results 59 6.1 Pre-Simulation and Post-Simulation 59 6.2 Measurement Environment Setup 61 6.3 Chip Micrograh 61 6.4 Measurement Results 62 6.4.1 Proposed 12-bit ADC 62 6.4.2 Column-Parallel 10-bit ADC w/o CIS 63 6.4.3 Column-Parallel 10-bit ADC w/ CIS 66 6.5 Performance Comparison 67 6.6 Summary 68 Chapter 7 Conclusion and Future Work 69 7.1 Conclusion 69 7.2 Future Work 69 Bibliography 71

    [1] T. Toyama et al., "A 17.7Mpixel 120fps CMOS image sensor with 34.8Gb/s readout," 2011 IEEE International Solid-State Circuits Conference, 2011, pp. 420-422.
    [2] I. Park, C. Park, J. Cheon and Y. Chae, "A 76mW 500fps VGA CMOS Image Sensor with Time-Stretched Single-Slope ADCs Achieving 1.95e- Random Noise," ISSCC, 2019, pp. 100-102.
    [3] D. Levski, M. Wäny and B. Choubey, "A 1- us Ramp Time 12-bit Column-Parallel Flash TDC-Interpolated Single-Slope ADC With Digital Delay-Element Calibration," TCAS I, 2019, pp. 54-67.
    [4] K. D. Choo et al., "Energy-Efficient Motion-Triggered IoT CMOS Image Sensor With Capacitor Array-Assisted Charge-Injection SAR ADC," JSSC, 2019, pp. 2921-2931.
    [5] T. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, 2nd ed.: WILEY, 2012.
    [6] R. J. Baker, CMOS: Circuit Design, Layout, and Simulation, 3rd ed.: WILEY, 2010
    [7] B. Razavi, Design of Analog CMOS Integrated Circuit, International ed., Boston: McGraw-Hill, 2010.
    [8] R. Funatsu et al., “133 Mpixel 60 fps CMOS image sensor with 32-column shared high-speed column-parallel SAR ADCs,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2015,pp. 1–3.
    [9] T. Arai, et al., “A 1.1μm 33Mpixel 240fps 3D-Stacked CMOS Image Sensor with 3-Stage Cyclic-Based Analog-to-Digital Converters,” ISSCC Dig. Tech.Papers, pp.126-127, Feb. 2016.
    [10] Q. Zhang, N. Ning, J. Li, Q. Yu, K. Wu and Z. Zhang, "A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors," in IEEE Access, vol. 8, pp. 172467-172480, 2020, doi: 10.1109/ACCESS.2020.3025153.
    [11] L. Sun, C.-T. Ko, K.-P. Pun, "Optimizing the Stage Resolution in Pipelined SAR ADCs for High-Speed High-Resolution Applications, " in IEEE Trans. Circuits Syst. II: Express Brilfs, vol. 61, no. 7, pp. 476-480, July 2014.
    [12] C. C. -M. Liu et al., "6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias," 2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, pp. 124-125.
    [13] T. Arai et al., "6.9 A 1.1µm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-to-digital converters," 2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, pp. 126-128.
    [14] Y. Oike et al., "An 8.3M-pixel 480fps global-shutter CMOS image sensor with gain-adaptive column ADCs and 2-on-1 stacked device structure," 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016, pp. 1-2
    [15] O. Kumagai et al., "A 1/4-inch 3.9Mpixel low-power event-driven back-illuminated stacked CMOS image sensor," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, pp. 86-88
    [16] H. Kim et al., "A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs," in IEEE Journal of Solid-State Circuits, vol. 51, no. 10, pp. 2262-2273
    [17] I. Park, W. Jo, C. Park, B. Park, J. Cheon and Y. Chae, "A 640 $\times$ 640 Fully Dynamic CMOS Image Sensor for Always-On Operation," in IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 898-907
    [18] K. Nie, W. Zha, X. Shi, J. Li, J. Xu and J. Ma, "A Single Slope ADC With Row-Wise Noise Reduction Technique for CMOS Image Sensor," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 9, pp. 2873-2882
    [19] Q. Zhang, N. Ning, J. Li, Q. Yu, Z. Zhang and K. Wu, "A High Area-Efficiency 14-bit SAR ADC With Hybrid Capacitor DAC for Array Sensors," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 12, pp. 4396-4408
    [20] Y. Nitta et al., "High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor," 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006, pp. 2024-2031
    [21] M. F. Snoeij, A. J. P. Theuwissen, K. A. A. Makinwa and J. H. Huijsing, "Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors," in IEEE Journal of Solid-State Circuits, vol. 42, no. 12, pp. 2968-2977
    [22] S. Lim, J. Lee, D. Kim and G. Han, "A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs," in IEEE Transactions on Electron Devices, vol. 56, no. 3, pp. 393-398
    [23] M. Kim, S. Hong and O. Kwon, "An Area-Efficient and Low-Power 12-b SAR/Single-Slope ADC Without Calibration Method for CMOS Image Sensors," in IEEE Transactions on Electron Devices, vol. 63, no. 9, pp. 3599-3604,
    [24] Y. Kim et al., "A 1/3-Inch 1.12μm-Pitch 13Mpixel CMOS Image Sensor with a Low-Power Readout Architecture," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-4
    [25] F. Tang, D. G. Chen, B. Wang and A. Bermak, "Low-Power CMOS Image Sensor Based on Column-Parallel Single-Slope/SAR Quantization Scheme," in IEEE Transactions on Electron Devices, vol. 60, no. 8, pp. 2561-2566
    [26] S. Xie and A. Theuwissen, "A 10 Bit 5 MS/s Column SAR ADC With Digital Error Correction for CMOS Image Sensors," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 6, pp. 984-988

    QR CODE