在今日的積體電路中，鎖相迴路是很廣泛的應用的設計元件。因其具有將時脈倍乘之功能，使其常常被放在通訊系統或微處理器上做時脈輸入的電路。但就如同多數電子元件一般,鎖相迴路亦會受到溫度變化,電壓不穩及其他雜訊之干擾,造成其輸出訊號產生時間上的偏移,產生時脈誤差.
傳統上的時脈誤差量測方法是使用外接之自動測試儀器對其做分析，只是自動測試儀器會對待測電路產生很大的負載，也會強迫晶片在設計時須多加額外之腳位供儀器做測試.。因此，近期很多直接設計於待測電路上的內建式自我測試電路被提出，包括時間-電壓轉換器、游標延遲線法、對偶斜率法等方法。可這些方法都需要一個沒有雜訊的理想訊號源作為比較對象,此訊號源是不易達成的。因此我們在此提出一個鎖相迴路的內建式自我測試電路,可解決需要理想訊號源的問題,又能達到很高的量測速度。
此量測過程分為三個部份： 單一週期取樣、粗調過程及微調過程等三個步驟來精確的量測雜訊的最大與最小值。粗調與細調的量測結果由兩個計數器所記錄著，此量測結果便可由計數器們的值而計算出。
校正過程：利用兩游標延遲線的時間差來計算兩次相位同步所需的震盪次數與所需時間，由這兩個值來得到電路實際製造後的時間延遲特性。
模擬與比較：此量測電路的可測頻率範圍為1.12GHz到2.2GHz，粗調時間為62.1ps，微調為7.98ps。使用HSPICE於COMS 0.18u，額定電壓為1.8V的製程下之模擬結果值，電路的解析度為7.98ps，最大誤差小於4ps，而量測時間為[11]的四分之一。

In this thesis, an on-chip circuit is proposed to measure the peak-to-peak values of worst-case period jitter in phase-locked loops (PLLs) and contains coarse-tune and fine-tune processes. The Coarse-tune process delays the previous rising edge about one clock period to compare with the next adjacent one. The fine-tune process increases or decreases a small timing difference between these adjacent edges to track the peak or valley values of jitter. The proposed circuit solves the problem that a jitter-free reference clock is required to measure the jitter.
The circuit is simulated by HSPICE with a 1.8V 0.18um CMOS process. The proposed circuit can operate at the range of 1.12GHz to 2.2GHz with resolution of 7.98ps and measurement error less than 4ps. Compared with other methods, the proposed circuit’s measuring speed is much faster (5 folds) with about 12.4% area overhead.

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