在超大型積體電路設計的過程中，常常會因為有新的規格或是違反了設計的限制而必須修改更正設計，我們將這個更正設計的過程稱為「工程變更」，通常是使用備用邏輯單元來協助解決工程變更的問題。晶片上有許多原來的設計沒有使用到的空間，備用邏輯單元就放在這些空間裡。在這篇論文中，我們提出了一個反覆產生技術映射答案的方法去找到對一個工程變更的問題合理的答案並且考慮到常數插入法的影響。所謂常數插入法是將備用邏輯單元的某些輸入與VDD或GND相接。而使用常數插入法可以提高備用邏輯單元在功能上的彈性，所以我們就不需要為了某些特定功能的邏輯單元而使用到太遠的備用邏輯單元。另外，我們還提出了一個選擇備用邏輯單元來組成技術映射答案的方法，並同時考慮到繞線或是時間的問題。而從我們的實驗結果顯示對於找到滿足合理的技術映射答案，使用常數插入法時所需要的範圍只有未使用常數插入法的百分之七十九，另外，使用常數插入法在繞線長度的減少量上最高可以達到百分之二十七。

In the VLSI design process, a design implementation often needs to be corrected because of new specifications or design constraint violations. This correction process is referred to as engineering change (EC). Usually, an EC problem is resolved by using spare cells, which have been inserted into the unused spaces of a chip. In this thesis, we propose an iterative method to generate feasible mapping solutions for an EC problem considering spare cells whose inputs may be tied to Vdd or Gnd, called constant insertion. Applying constant insertion can increase the cells’ flexibility in aspect of functionalities, so we do not necessarily have to use far-away cells just for some specific types. In addition, we propose a method to construct a mapping solution using spare cells considering routing or timing issues. Our experimental results show that the area required to find a feasible mapping solution with constant insertion is only 79% of the area without using constant insertion, and the wire length reduction with constant insertion is up to 27%.

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