統計時序分析(statistical static timing analysis, SSTA)在會產生變異的奈米製程(nanometer manufacturing)底下是不可或缺的，而當製程會導致成品明顯變異時，將使得超大型積體電路的時序預測成為一個困難的挑戰。統計時序分析非常適合應用在當製程變異時，預測電路成品的時序以及量產可行性設計上。然而大部分的統計時序分析技術若要維持最大值運算(max operation)與加法運算(sum operation)後的封閉形式(closed-form)表示法是很困難的，為了計算一個最大值運算以及加法運算後的統計封閉形式表示法，我們由前人提出的一次串接形式表示法(first-order canonical form)與偏斜常態分布(skew-normal distribution)獲得了靈感，提出了一個解析的方法去解決這個問題。這個解決的方法不但是封閉形式的，並且當時序來源是常態分布時的結果很精確。我們的實驗結果證明了這一點，當與蒙地卡羅模擬(Monte-Carlo simulation)的結果比較時，我們的方法估算時序限制(timing constraint)的誤差在1.5%以內；預測良率(yield)的誤差在0.2%以內。

Statistical static timing analysis (SSTA) is indispensable for nanometer manufacturing under process variability.
The process variations cause significant uncertainty in VLSI circuit timing and this makes yield control and timing verification a very difficult challenge.
SSTA is suitable for timing estimation and design for manufacturability under process variation.
However, most of the existing SSTA techniques have difficulty in keeping closed-form expressions after max operations and sum operations on variation sources.
For computing a converged statistical form after max operations and sum operations, we propose an analytical approach which innovates the concept given by first-order canonical form and skew-normal distribution to solve this problem.
These derived results are in closed-form and precise when timing sources have the skew-normal distribution or normal distribution.
Experimental results show that, compared to the Monte-Carlo simulation, our approach estimates the timing constraint and predicts the yield within 1.5% and 0.2% error, respectively.

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