本研究的主要目的在於建構正確之覆晶球形陣列封裝之表面熱傳係數，進而當做三維熱傳程式之邊界條件，來大幅降低計算時間。首先，藉由熱流分析軟體FLOTHERM，模擬覆晶球型陣列封裝在不同材料性質和不同基板大小下，且測試條件是層流和強制對流（忽略熱幅射和重力效應)狀況下之熱傳現象，進一步採用FLOTHERM的結果，得到封裝接觸到流體之表面之熱傳係數，此新的熱傳係數關係式，能包含材料和基板的效應。
此一組新的熱傳係數關係式，將被使用為三維熱傳導程式之邊界條件，取代一般的平板公式。且由於封裝幾何形狀的關係，有四個重要的表面熱傳係數需要考慮，分別是晶片上表面和基板上表面和印刷電路板上下表面之熱傳係數。接下來，我們藉著最佳化擬合去計算在固定基板大小下，不同材料性質下四個表面熱傳係數的值。此外由三維熱導傳程式的值顯示，使用平板公式的為邊界條件下的接點溫度誤差隨著風速的增加最大可到１２％，但是隨著封裝元件的熱傳導係數增加，最大的接點溫度誤差小於３％，但是使用新的熱傳係數為邊界條件下的最大接點溫度誤差小於１％，因此當計算的精確度要求很嚴格的狀況下，建議使用新的熱傳係數關係式，以減少計算誤差。

The main objective of the present study is to construct a heat transfer correlation to be used as boundary condition in the three-dimensional conduction simulation to simulate the thermal field within the flip chip BGA package. First, the thermal field of the flip chip BGA package is simulated using CFD model under the laminar flow regime, where the radiant and gravitational effects are ignored, and the simulated results are used to extract the heat transfer coefficients along the surfaces in contact with the airflow. Then, based on the heat transfer coefficients, a new group of accurate heat transfer coefficients correlations that include the effects of different substrate sizes and package components thermal conductivities is proposed.
This will be used as the boundary conditions for the three dimensional conduction equation to replace the commonly adopted flat plate formula. Due to the package geometry configuration, there are four important local heat transfer coefficients needed to be considered. They are Hdie, Hsub, Hpcbup, Hpcbdown, which mean the heat transfer coefficients on the surface of the die, substrate, upper surface of PCB and lower surface of PCB, respectively. A best fitting interpolation procedure is applied to determine the Hsub, Hpcbup, and Hpcbdown under different thermal component conductivities, when the substrate size is fixed.

Three-dimensional conduction simulations for flip-chip BGA package using the flat plate formula indicates that when the free stream velocity increases the maximum predicted junction temperature error increases up to 12 %. However, when the components thermal conductivities increase, the maximum predicted error decreases down to 3 %. If the newly developed heat transfer coefficients correlations are used as boundary condition in the 3-D conduction simulations of the flip-chip BGA package, the maximum predicted junction temperature error is less than 1 %. Therefore, if the requirement of simulation accuracy is very restrict, it is not advisable to use the flat plate formula to predict the heat transfer coefficients h, instead the newly proposed formula should be adopted.

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