接觸點電阻轉換之研究: 電阻式記憶體及其應用

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研究生：	沈文超 Shen, Wen-Chao
論文名稱：	接觸點電阻轉換之研究: 電阻式記憶體及其應用 The Study of Contact Resistive Switching Behavior: RRAM and Its Application
指導教授：	林崇榮 Lin, Chrong-Jung
口試委員:	林崇榮金雅琴蔡銘進翁烔城楊青松
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2014
畢業學年度：	103
語文別：	英文
論文頁數：	140
中文關鍵詞：	電阻式記憶體、非揮發性邏輯閘、隨機亂數產生器、垂直式雙極性接面電晶體
外文關鍵詞：	RRAM, NV Latch, Random Number Generator, Vertical BJT
相關次數：	點閱：3 下載：0
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在過去數十年間，歸功於個人攜帶式設備及雲端科技的發展，爆炸性成長的儲存需求不斷刺激各種固態儲存的創新研發。快閃記憶體是現今應用於大量資料儲存的主流產品並且長期占據市場中的領先地位。然而，快閃記憶體也面臨著在製程微縮上各式各樣的挑戰與困難，包括高電壓電路設計、薄膜可靠度，已及日漸增加的製程複雜度。學術界及工業界都在引頸期盼一個泛用的解決方案作為未來固態儲存的技術。電阻式記憶體有著優異的特性包括快速寫入數度，製程簡易，元件結構單純以及高度相容於邏輯製程，似乎有望在未來固態儲存領域扮演救世主的角色。在本論文中，一種新型的接觸點式電阻式記憶體已經被研究並且量測分析。此元件的電阻轉換特性可以在從0.18微米到28奈米的邏輯製程中實現並且觀測。隨著製程技術的演變，它展現了優異的微縮特性，在內嵌式系統單晶片應用上將可望是潛在的解決方案。除此之外，在邏輯製程發展下的垂直式雙極性電晶體將做為接觸點電阻式記憶體的選擇元件，藉此實現超高密度的記憶體陣列。電阻轉換特性在過去幾年也被廣泛研究在非傳統儲存應用上面，譬如利用電阻式記憶體模擬腦內神經傳導，設計具有學習能力的仿神經電路，這些領域具有高度的創新性，並且在未來有著更龐大的發展潛能。本論文基於對於接點式電阻式記憶體的了解及研究經驗，發展一種非揮發性邏輯閘及隨機亂數產生器。利用順序性的輸入訊號配合共用接點的結構，非揮發性邏輯閘具備有計算AND或是OR能力，並且同時記憶輸出值的功能。而隨機亂數產生器則是利用簡單的比較電路，可以產生隨機零或壹數位訊號，而這些隨機亂數的數位訊號將可以作為通訊加密使用。總歸而言，接點式電阻記憶體有著很多優異的元件特性，並且可以在純邏輯製程中製作完成，而垂直式新型雙極性電晶體則可以更進一步的縮小單一記憶位元的面積，最後，利用接觸點電阻式記憶體的特性，本論文發展兩種不同於傳統記憶體的應用

Abstract During a past decade, the explosive increase on storage demand, including personal portable device and cloud technology, has spurred a kaleidoscope of investigation and development on solid state storage. The main-stream technology for fast and mass data storage nowadays, flash memory, has long-time occupied the leading position in the market. It, however, suffered a series of wide spectrums of scaling challenge, such as high voltage design, thin film reliability and process complexity. Scientists and industry are looking forward a universal solution as alternative for solid-state storage in the future. Resistive Random Access Memory, with the superior characteristic on writing speed, simplicity on structure and process, and highly compatible to CMOS process, seems like a promising savior in the future. In this dissertation, the Contact Random Access Memory (CRRAM) has been fully studied and characterized. The resistive switching behavior of CRRAM has been observed from 0.18m technology to advanced 28nm node in standard CMOS logic process. It shows the continuous scaling ability in both unit cell size and applied voltage, promising the CRRAM as a potential candidate in the field of embedded SOC application. Furthermore, ultra-high density CRRAM array can be realised by introduction of logic compatible vertical bipolar junction transistor (VBJT). With burying the NPN junction as conductive selector in the silicon substrate, single Contact RRAM (1C-RRAM) is demonstrated. Study of resistive switching phenomenon in the past few years reveals its widely application beyond memory. Including RRAM-base synapse to simulate and implement neuromorphic circuit and element-based logic operation. These areas are novel and attractive with infinity possibility in near future. Basing on the study and observation of CRRAM, this dissertation proposes two novel applications beyond conventional memory. Firstly, the share contact structure with properly input sequential signal to realise a non-volatile logic operation gate. Secondly, a novel true random number generator has been realised base on the strong random telegraph noise in CRRAM. In summary, CRRAM has several attractive advantage and superior cell performances including fully compatible with CMOS process and platform, ultra-small cell size, data retention and endurance. Its cell size can be further reduced by introduction of Vertical BJT as array selector. Finally, two unique inventions based on resistive switching behavior and strong noise in RRAM current are demonstrated. These shows the CRRAM could not only be a promising candidate for embedded memory, but also could implement as special circuit application.

List of Contents
中文摘要          i
Abstract           iii
Acknowledgement   v
List of Contents     viii
List of Figures      x
Chapter 1    Introduction   1
1    Challenges to conventional charge-based nonvolatile memory   2
2    Introduction to next generation memory   5
3    Dissertation Organisation    6
Chapter 2    Reviews of Resistive Switching Memories   8
1    Phase change memory   9
2    Resistive random access memory   11
3    Memory selector   14
4    Summary    17
Chapter 3    CRRAM in Advanced High-K Metal Gate CMOS Technology  26
1    Structure and fabrication  27
2    Operation Principle  30
3    Optimal Contact Design  33
4    Read Operation and Stability  35
5    Reliability Characteristic  37
6    CRRAM Scaling Trend: Challenge and Opportunity  38
7    Summary  40
Chapter 4    Single Contact Structure with Bipolar Junction Transistor  58
1    Fabrication of a CMOS-based bipolar junction transistor  59
2    BJT characteristics  62
2.1    Gummel plot and breakdown voltage  64
3    1C-CRRAM in 65 nm pure CMOS technology  67
3.1    Array schematic and layout  67
3.2    Operation principle  68
3.3    Read and reliability  69
4    Summary  70
Chapter 5    Memristor-Base Application beyond Memory  100
1    Memristor logic operation gate  101
1.1    Share contact structure  101
1.2    Operation principle  103
1.3    Results and discussion  105
1.4    Summary  107
2    CRRAM-based true random number generator  107
2.1    Random telegraph noise observation on RRAM  108
2.2    True random number generator structure  110
2.3    Results and discussion  111
2.4    Summary  114
Chapter 6    Conclusion  133
1    Conclusion  133
2    Future Work  133


                                

Reference
[1] Chua L. O., "Memristor-The missing circuit element," Circuit Theory, IEEE Transactions on, vol. 18, pp. 507-519, 1971.
[2] Strukov D. B., Snider G. S., Stewart D. R., and Williams R. S., "The missing memristor found," Nature, vol. 453, pp. 80-3, May 1 2008.
[3] Gao B., Yu S., Xu N., Liu L. F., Sun B., Liu X. Y., Han R. Q., Kang J. F., Yu B., and Wang Y. Y., "Oxide-based RRAM switching mechanism: A new ion-transport-recombination model," in Electron Devices Meeting, 2008. IEDM 2008. IEEE International, 2008, pp. 1-4.
[4] Chen Y. S., Lee H. Y., Chen P. S., Gu P. Y., Chen C. W., Lin W. P., Liu W. H., Hsu Y. Y., Sheu S. S., Chiang P. C., Chen W. S., Chen F. T., Lien C. H., and Tsai M. J., "Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity," in Electron Devices Meeting (IEDM), 2009 IEEE International, 2009, pp. 1-4.
[5] Cheng C. H., Tsai C. Y., Chin Albert, and Yeh F. S., "High performance ultra-low energy RRAM with good retention and endurance," in Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 19.4.1-19.4.4.
[6] Ho C.H., Hsu C.L., Chen C.C., Liu J.T., Wu C.S., Huang C.C., Hu C., and Yang F.L., "9nm Half-Pitch Functional Resistive Memory Cell with <1A Programming Current Using Thermally Oxidized Sub-Stoichiometric WOx Film," in Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 19.1.1-19.1.4.
[7] Chien W. C., Chen Y. C., Lai E. K., Yao Y. D., Lin P., Horng S. F., Gong J., Chou T. H., Lin H. M., Chang M. N., Shih Y. H., Hsieh K. Y., Liu R., and Chih-Yuan Lu, "Unipolar Switching Behaviors of RTO WOX RRAM," Electron Device Letters, IEEE, vol. 31, pp. 126-128, 2010.
[8] Lee D., Seong D.J., Choi H.J., Jo I., Dong R., Xiang W., Seokjoon Oh, Pyun M., Seo S., Heo S., Jo M., Hwang D.K., Park H. K., Chang M., Hasan M., and Hwang H., "Excellent uniformity and reproducible resistance switching characteristics of doped binary metal oxides for non-volatile resistance memory applications," in Electron Devices Meeting, 2006. IEDM '06. International, 2006, pp. 1-4.
[9] Fang Z., Yu H. Y., Liu W. J., Wang Z. R., Tran X. A., Gao B., and Kang J. F., "Temperature Instability of Resistive Switching on HfOx-Based RRAM Devices," Electron Device Letters, IEEE, vol. 31, pp. 476-478, 2010.
[10] Kim H.D., An H.M., and Tae G. K., "Improved reliability of Au/Si3N4/Ti resistive switching memory cells due to a hydrogen postannealing treatment," Journal of Applied Physics, vol. 109, pp. 016105-016105-3, 2011.
[11] Ielmini D., Spiga S., Nardi F., Cagli C., Lamperti A., Cianci E., and Fanciulli M., "Scaling analysis of submicrometer nickel-oxide-based resistive switching memory devices," Journal of Applied Physics, vol. 109, pp. 034506-034506-8, 2011.
[12] Kim D. C., Seo S., Ahn S. E., Suh D. S., Lee M. J., Park B. H., Yoo I. K., Baek I. G., Kim H. J., Yim E. K., Lee J. E., Park S. O., Kim H. S., Chung U. in, Moon J. T., and Ryu B. I., "Electrical observations of filamentary conductions for the resistive memory switching in NiO films," Applied Physics Letters, vol. 88, pp. 202102-202102-3, 2006.
[13] Kim M. J., Baek I. G., Ha Y. H., Baik S. J., Kim J. H., Seong D. J., Kim S. J., Kwon Y. H., Lim C. R., Park H. K., Gilmer D., Kirsch P., Jammy R., Shin Y. G., Choi S., and Chung C., "Low power operating bipolar TMO ReRAM for sub 10 nm era," in Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 19.3.1-19.3.4.
[14] Lee H. Y., Chen P. S., Wu T. Y., Chen Y. S., Wang C. C., Tzeng P. J., Lin C. H., Chen F., Lien C. H., and Tsai M. J., "Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM," in Electron Devices Meeting, 2008. IEDM 2008. IEEE International, 2008, pp. 1-4.
[15] Lee H. Y., Chen Y. S., Chen P. S., Gu P. Y., Hsu Y. Y., Wang S. M., Liu W. H., Tsai C. H., Sheu S. S., Chiang P. C., Lin W. P., Lin C. H., Chen W. S., Chen F. T., Lien C. H., and Tsai M., "Evidence and solution of Over-RESET Problem for HfOX Based Resistive Memory with Sub-ns Switching Speed and High Endurance," in Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 19.7.1-19.7.4.
[16] Lee H. Y., Chen Y. S., Chen P. S., Wu T. Y., Chen F., Wang C. C., Tzeng P. J., Tsai M. J., and Lien C., "Low-Power and Nanosecond Switching in Robust Hafnium Oxide Resistive Memory With a Thin Ti Cap," Electron Device Letters, IEEE, vol. 31, pp. 44-46, 2010.
[17] Russo U., Ielmini D., Cagli C., and Lacaita A. L., "Filament Conduction and Reset Mechanism in NiO-Based Resistive-Switching Memory (RRAM) Devices," Electron Devices, IEEE Transactions on, vol. 56, pp. 186-192, 2009.
[18] Seo S., Lee M. J., Seo D. H., Jeoung E. J., Suh D. S., Joung Y. S., Yoo I. K., Hwang I. R., Kim S. H., Byun I. S., Kim J. S., Choi J. S., and Park B. H., "Reproducible resistance switching in polycrystalline NiO films," Applied Physics Letters, vol. 85, pp. 5655-5657, 2004.
[19] Kim S. and Choi Y.-K., "A Comprehensive Study of the Resistive Switching Mechanism in Al/TiOx/TiO2/Al-Structured RRAM," Electron Devices, IEEE Transactions on, vol. 56, pp. 3049-3054, 2009.
[20] Tseng Y.H., Huang C.-E, Kuo C. H., Chih Y. D., and Lin C.-J., "High density and ultra small cell size of Contact ReRAM (CR-RAM) in 90nm CMOS logic technology and circuits," in Electron Devices Meeting (IEDM), 2009 IEEE International, 2009, pp. 1-4.
[21] Tsunoda K., Kinoshita K., Noshiro H., Yamazaki Y., Iizuka T., Ito Y., Takahashi A., Okano A., Sato Y., Fukano T., Aoki M., and Sugiyama Y., "Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3 V," in Electron Devices Meeting, 2007. IEDM 2007. IEEE International, 2007, pp. 767-770.
[22] Shen W.C., Tseng Y.H., Chih Y. D., and Lin C.-J., "Memristor Logic Operation Gate With Share Contact RRAM Cell," IEEE Electron Device Lett., vol. 32, pp. 1650-1652, 2011.
[23] Okamoto K., Tada M., Sakamoto T., Miyamura M., Banno N., Iguchi N., and Hada H., "Conducting mechanism of atom switch with polymer solid-electrolyte," in Electron Devices Meeting (IEDM), 2011 IEEE International, 2011, pp. 12.2.1-12.2.4.
[24] Tseng Y.-H., Shen W.C., Hunag C.-E., Lin C.-J., and King Y.C., "Electron trapping effect on the switching behavior of contact RRAM devices through random telegraph noise analysis," in Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 28.5.1-28.5.4.
[25] Cagli C., Buckley J., Jousseaume V., Cabout T., Salaun A., Grampeix H., et al., "Experimental and theoretical study of electrode effects in HfO¬2 based RRAM," in Electron Devices Meeting (IEDM), 2011 IEEE International, 2011, pp. 28.7.1-28.7.4.
[26] Tseng Y.-H., Shen W.C., and Lin C.-J., "Modeling of electron conduction in contact resistive random access memory devices as random telegraph noise," Journal of Applied Physics, vol. 111, pp. 073701-073701-5, 2012.
[27] Gao B., Kang J. F., Chen Y. S., Zhang F. F., Chen B., Huang P., Liu L. F., Liu X. Y., Wang Y. Y., Tran X. A., Wang Z. R., Yu H. Y., and Chin Albert, "Oxide-based RRAM: Unified microscopic principle for both unipolar and bipolar switching," in Electron Devices Meeting (IEDM), 2011 IEEE International, 2011, pp. 17.4.1-17.4.4.
[28] Chen B., Lu Y., Gao B., Fu Y. H., Zhang F. F., Huang P., Chen Y. S., Liu L. F., Liu X. Y., Kang J. F., Wang Y. Y., Fang Z., Yu H. Y., Li X., Wang X. P., Singh N., Lo G. Q., and Kwong D. L., "Physical mechanisms of endurance degradation in TMO-RRAM," in Electron Devices Meeting (IEDM), 2011 IEEE International, 2011, pp. 12.3.1-12.3.4.
[29] Wuttig M. and Yamada N., "Phase-change materials for rewriteable data storage," Nature Materials, vol. 6, pp. 824-832, 2007.
[30] Fang T.-N., Kaza S., Haddad S., Chen A., Wu Y.-C., Lan Z., Avanzino S., Liao D., Gopalan C., Choi S., Mahdavi S., Buynoski M., Lin Y., Marrian C., Bill C., VanBuskirk M., and Taguchi M., "Erase mechanism for copper oxide resistive switching memory cells with nickel electrode," in Electron Devices Meeting, 2006. IEDM '06. International, 2006.
[31] Chen A., Haddad S., Wu Y. C., Fang T. N., Kaza S., and Lan Z., "Erasing characteristics of Cu2O metal-insulator-metal resistive switching memory," Applied Physics Letters, vol. 92, p. 013503, 2008.
[32] Akinaga H. and Shima H., "Resistive Random Access Memory (ReRAM) Based on Metal Oxides," Proceedings of the IEEE, vol. 98, pp. 2237-2251, 2010.
[33] Wong H. S. P., Lee H.Y., Yu S., Chen Y.S., Wu Y., Chen P.-S., Lee B., Chen F. T., and Tsai M.-J., "Metal-Oxide RRAM," Proceedings of the IEEE, vol. 100, pp. 1951-1970, 2012.
[34] Kim W., Park S. I., Zhang Z., Young Y.-L., Sekar D., Wong H. S. P., and Wong S. S., "Forming-free nitrogen-doped AlOX RRAM with sub-A programming current," in VLSI Technology (VLSIT), 2011 Symposium on, 2011, pp. 22-23.
[35] Yi Wu, Lee B., and Wong H. S. P., " Al2O3-Based RRAM Using Atomic Layer Deposition (ALD) With 1-A RESET Current," Electron Device Letters, IEEE, vol. 31, pp. 1449-1451, 2010.
[36] Myoung-Jae Lee, Youngsoo Park, Bo-Soo Kang, Seung-eon Ahn, Changbum Lee, Kihwan Kim, Wenxu Xianyu, Stefanovich G., Jung-Hyun Lee, Seok-Jae Chung, Yeon-Hee Kim, Chang-Soo Lee, Jong-Bong Park, and In-Kyeong Yoo, "2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications," in Electron Devices Meeting, 2007. IEDM 2007. IEEE International, 2007, pp. 771-774.
[37] Linn Eike, Rosezin Roland, Kügeler Carsten, and Waser Rainer, "Complementary resistive switches for passive nanocrossbar memories," Nature Materials, vol. 9, pp. 403-406, 2010.
[38] Yalon E., Gavrilov A., Cohen S., Mistele D., Meyler B., Salzman J., and Ritter D., "Resistive Switching in HfO2 Probed by a Metal-Insulator-Semiconductor Bipolar Transistor," Electron Device Letters, IEEE, vol. 33, pp. 11-13, 2012.
[39] Yalon E., Elias D. C., Gavrilov A., Cohen S., Halevy R., and Ritter D., "A Degenerately Doped In0.53Ga0.47As Bipolar Junction Transistor," Electron Device Letters, IEEE, vol. 32, pp. 21-23, 2011.
[40] Lin C.C., Lin C.-Y., Lin M.-H., Lin C.-H., and Tseng T.-Y., "Voltage-Polarity-Independent and High-Speed Resistive Switching Properties of V-Doped SrZrO3 Thin Films," Electron Devices, IEEE Transactions on, vol. 54, pp. 3146-3151, 2007.
[41] Baek I. G., Kim D. C., Lee M. J., Kim H. J., Yim E. K., Lee M. S., Lee J. E., Ahn S. E., Seo S., Lee J. H., Park J. C., Cha Y. K., Park S. O., Kim H. S., Yoo I. K., Chung U. In, Moon J. T., and Ryu B. I., "Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application," in Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, 2005, pp. 750-753.
[42] Chevallier C. J., Chang H.S., Lim S. F., Namala S. R., Matsuoka M., Bateman B. L., and Rinerson D., "A 0.13m 64Mb multi-layered conductive metal-oxide memory," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, 2010, pp. 260-261.
[43] Nardi F., Cagli C., Spiga S., and Ielmini D., "Reset Instability in Pulsed-Operated Unipolar Resistive-Switching Random Access Memory Devices," Electron Device Letters, IEEE, vol. 32, pp. 719-721, 2011.
[44] Yu S., Guan X., and Wong H. S. P., "On the stochastic nature of resistive switching in metal oxide RRAM: Physical modeling, monte carlo simulation, and experimental characterization," in Electron Devices Meeting (IEDM), 2011 IEEE International, 2011, pp. 17.3.1-17.3.4.
[45] Kim S., Choi S.-J., and Choi Y.-K., "Resistive-Memory Embedded Unified RAM (R-URAM)," Electron Devices, IEEE Transactions on, vol. 56, pp. 2670-2674, 2009.
[46] Jo S. H., Chang T., Ebong I., Bhadviya B. B., Mazumder P., and Lu W., "Nanoscale memristor device as synapse in neuromorphic systems," Nano letters, vol. 10, pp. 1297-301, Apr 14 2010.
[47] Versace M. and Chandler B., "The brain of a new machine," Spectrum, IEEE, vol. 47, pp. 30-37, 2010.
[48] Fei W., Yu H., Zhang W., and Yeo K.S., "Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 20, pp. 1012-1025, 2012.
[49] Fujita S., Uchida K., Yasuda S., Ohba R., Nozaki H., and Tanamoto T., "Si nanodevices for random number generating circuits for cryptographic security," in Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International, 2004, pp. 294-295 Vol.1.
[50] Brederlow R., Prakash R., Paulus C., and Thewes R., "A low-power true random number generator using random telegraph noise of single oxide-traps," in Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International, 2006, pp. 1666-1675.
[51] Srinivasan S., Mathew S., Erraguntla V., and Krishnamurthy R., "A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS," in VLSI Design, 2009 22nd International Conference on, 2009, pp. 301-306.
[52] Matsumoto M., Yasuda S., Ohba Ryuji, Ikegami K., Tanamoto T., and Fujita Shinobu, "1200m2 Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application," in Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, 2008, pp. 414-624.
[53] Chang C. M., Chung S. S., Hsieh Y. S., Cheng L. W., Tsai C. T., Ma G. H., Chien S. C., and Sun S. W., "The observation of trapping and detrapping effects in high-k gate dielectric MOSFETs by a new gate current Random Telegraph Noise (IG-RTN) approach," in Electron Devices Meeting, 2008. IEDM 2008. IEEE International, 2008, pp. 1-4.
[54] Ielmini D., Nardi F., and Cagli C., "Resistance-dependent amplitude of random telegraph-signal noise in resistive switching memories," Applied Physics Letters, vol. 96, pp. 053503-053503-3, 2010.
[55] Petrie C. S. and Connelly J. A., "A noise-based IC random number generator for applications in cryptography," Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on, vol. 47, pp. 615-621, 2000.
[56] Terai M., Sakotsubo Y., Saito Y., Kotsuji S., and Hada H., "Memory-State Dependence of Random Telegraph Noise of Ta2O5/TiO2 Stack ReRAM," Electron Device Letters, IEEE, vol. 31, pp. 1302-1304, 2010.

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