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研究生: 吳俊賢
Wu, Chun-Hsien
論文名稱: 具4X4電極陣列之CMOS-MEMS神經感測探針
CMOS-MEMS Neural Recording Probes with 4x4 Microelectrodes
指導教授: 盧向成
Lu, Shiang-Cheng
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2010
畢業學年度: 98
語文別: 中文
論文頁數: 92
中文關鍵詞: 微機電系統神經感測探針電壓緩衝器多工器運算放大器深反應離子蝕刻
外文關鍵詞: MEMS (Micro-Electro-Mechanical System), Neural recording probe, Voltage buffer, Multiplexer, Operational amplifier, Deep reaction ion etch
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  •   本論文旨在利用製程廠現有CMOS積體電路製程技術(TSMC 0.35 □um CMOS process)與微機電系統(Micro-Electro-Mechanical System, MEMS)整合,經適當後製程處理完成一新穎CMOS MEMS神經感測探針之製作。與一般微機電不同的是,我們在前端設計了電壓緩衝器(Voltage Buffer)與感測電極陣列結合,以達到減少訊號失真與降低導線連接時所產生之寄生電容的目的,而為了減少I/O PAD數目,我們還設計一16:1的多工器(Multiplexer, MUX)於緩衝器之輸出端,使得原本龐大的陣列輸出最後只需一個Output PAD即可,而最後一級為運算放大器(Operational Amplifier, OP-amp),經由MUX輸出的神經訊號將在此處被放大。
      在後製程處理過程中,使用薄膜沉積技術成長生物相容性佳之金屬於電極上方以傳導神經訊號,並利用鉻(Cr)金屬定義探針形狀與作為蝕刻矽基材和二氧化矽時之蝕刻抵擋層,最後以深反應離子蝕刻(Deep Reaction Ion Etch, Deep RIE)系統蝕刻出探針結構。所設計之前端電壓緩衝器架構為共汲極放大器(源極隨偶器),於緩衝器輸入端中有一可調式一階高通濾波器用以設定輸入直流準位及濾除低頻雜訊,而多工器的設計則是採用傳輸閘(transmission gate)架構作為訊號選擇的路徑,最後的放大器為具頻率補償之兩級式運算放大器,其具備了高增益與低雜訊的特點。


    The goal of this thesis is using CMOS integrated circuit (IC) technology (TSMC 0.35 □m CMOS process) to combine with MEMS technology for implementing a novel CMOS-MEMS neural recording probe with suitable die-level post-fabrication. We design a voltage sensing buffer and construct a sensing electrode array with minimized parasitic effect. In order to reduce the number of I/O pad, the 16-to-1 multiplexer has been realized such that the total amount of output pads can be minimized. The last stage is an operational amplifier, which is used to amplify the neural signals.
      During the post-fabrication, we use the thin-film technique to grow a biocompatible metal layer on electrode sites for detecting the neural signals. A chromium mask is used for defining the probe shape and as an etch-protection layer when we remove the silicon substrate and silicon dioxide layer. Finally, the probe is released by using a deep reaction ion etch. The voltage buffer is a common-drain amplifier (source follower), and we design a passive tunable first-order high pass filter at input node to set the dc-bias for the amplifier and to reject low frequency noise. Furthermore, the switch is built based on the transmission gate in our multiplexer. The gain stage is two-stage frequency compensation operational amplifier, it has a high gain and a low noise characteristic.

    摘要-------------------------------------------------------I Abstract--------------------------------------------------II 致謝------------------------------------------------------IV 目錄-------------------------------------------------------V 圖目錄---------------------------------------------------VII 表目錄-----------------------------------------------------X 第一章 序論 ---------------------------------------1 1.1 微機電系統技術 -----------------------------1 1.2 神經元與神經感測探針 -------------------2 1.3 文獻回顧 ---------------------------------------5 1.4 研究動機與論文概述 ----------------------------14 第二章 CMOS-MEMS 神經感測探針之設計 ------------------16 2.1 CMOS-MEMS神經感測探針之架構 ------------------16 2.2 源極隨耦器之設計與模擬 ------------------17 2.2.1 大訊號與小訊號分析 ----------------------------17 2.2.2 設計與模擬結果 ----------------------------22 2.3 16:1多工器之設計與模擬 ------------------34 2.4 電容回授式運算放大器之設計與模擬 --------37 2.4.1 運算放大器之分析 ----------------------------37 2.4.2 運算放大器之設計與模擬結果 ------------------41 2.4.3 輸出緩衝級 ----------------------------55 2.5 感測電路Layout與後模擬 ------------------57 2.6 神經感測探針之後製程設計 ------------------60 2.6.1 探針結構之後製程設計 ------------------60 2.6.2 神經感測探針之Layout ------------------62 第三章 神經感測探針之後製程 ------------------64 3.1 正面鉻金屬遮罩層之製作 ------------------64 3.2 感測探針之正面蝕刻 ----------------------------66 3.3 背蝕刻與探針結構釋放 ------------------68 3.4 金屬接點釋放與感測電極沉積 ------------------71 第四章 量測結果 --------------------------------------78 4.1 感測電路之量測 ----------------------------78 4.2 神經感測探針之量測 ----------------------------83 第五章 結論 --------------------------------------88 參考文獻 ------------------------------------------------89

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