我們提出了一個重新映射演算法能容忍單晶片網路之多處理器系統的處理元件(PE）的錯誤。一個新的圖型建模被提出來以精確定義重新映射後的PE之間的溝通成本的變化量。我們的方法不僅可以用於修復PE故障，而且能改善給定的初始映射的溝通成本。實驗結果顯示，在多個PE錯誤下使用相同數量的備用PE，我們的方法比以前的方法[1]的溝通成本平均下降了43.59％。此外，我們的方法應用在由NMAP[2]產生初始映射後更進一步地減少了4.16％。

We propose a remapping algorithm to tolerate the failures of Processing Elements (PEs) on Multiprocessor System-on-Chip. A new graph modeling is proposed to precisely define the increase of communication cost among PEs after remapping. Our method can be used not only to repair faults but also to improve the communication cost of given initial mapping results​. Experimental results show that under multiple failures, the communication cost by our method is 43.59\% less on average compared with that by previou​s work [1] using the same ​number of ​spare PEs. Moreover, the communication cost is further reduced by 4.16\% after applying our method ​to​ initial mappings produced by NMAP [2].

[1] Leibo Liu, Yu Ren, Chenchen Deng, Shouyi Yin, Shaojun Wei, and Jie Han. A
novel approach using a minimum cost maximum
ow algorithm for fault-tolerant
topology reconguration in noc architectures. In Design Automation Conference
(ASP-DAC), 2015 20th Asia and South Pacic, pages 48{53. IEEE, 2015.
[2] Srinivasan Murali and Giovanni De Micheli. Bandwidth-constrained mapping of
cores onto noc architectures. In Proceedings of the conference on Design, automation
and test in Europe-Volume 2, page 20896. IEEE Computer Society, 2004.
[3] Jorg Henkel, Wayne Wolf, and Srimat Chakradhar. On-chip networks: A scalable,
communication-centric embedded system design paradigm. In VLSI Design, 2004.
Proceedings. 17th International Conference on, pages 845{851. IEEE, 2004.
[4] Antonio Pullini, Federico Angiolini, Davide Bertozzi, and Luca Benini. Fault tolerance
overhead in network-on-chip
ow control schemes. In Integrated Circuits and
Systems Design, 18th Symposium on, pages 224{229. IEEE, 2005.
[5] Cristinel Ababei and Rajendra Katti. Achieving network on chip fault tolerance
by adaptive remapping. In Parallel & Distributed Processing, 2009. IPDPS 2009.
IEEE International Symposium on, pages 1{4. IEEE, 2009.
[6] Onur Derin, Deniz Kabakci, and Leandro Fiorin. Online task remapping strategies
for fault-tolerant network-on-chip multiprocessors. In Proceedings of the Fifth
29
ACM/IEEE International Symposium on Networks-on-Chip, pages 129{136. ACM,
2011.
[7] Pradip Kumar Sahu, Nisarg Shah, Kanchan Manna, and Santanu Chattopadhyay.
A new application mapping algorithm for mesh based network-on-chip design. In
India Conference (INDICON), 2010 Annual IEEE, pages 1{4. IEEE, 2010.
[8] Pradip Kumar Sahu and Santanu Chattopadhyay. A survey on application mapping
strategies for network-on-chip design. Journal of Systems Architecture, 59(1):60{76,
2013.
[9] Amit Kumar Singh, Muhammad Shaque, Akash Kumar, and Jorg Henkel. Mapping
on multi/many-core systems: survey of current and emerging trends. In Pro-
ceedings of the 50th Annual Design Automation Conference, page 1. ACM, 2013.
[10] Lasse Lehtonen. Transaction generator-tool for network-on-chip benchmarking.
2014.
[11] Jingcao Hu, Umit Y Ogras, and Radu Marculescu. System-level buer allocation
for application-specic networks-on-chip router design. IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems, 25(12):2919{2933,
2006.
[12] Weichen Liu, Jiang Xu, Xiaowen Wu, Yaoyao Ye, Xuan Wang, Wei Zhang, Mahdi
Nikdast, and Zhehui Wang. A noc trac suite based on real applications. In 2011
IEEE Computer Society Annual Symposium on VLSI, pages 66{71. IEEE, 2011.