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研究生: 李茂麟
Mao Lin Lee
論文名稱: 應用於NAND型快閃式記憶體之多重頁編碼模式研究
A Multiple Page Programming Scheme in NAND Type Flash Memory
指導教授: 徐清祥
Dr. Charles Ching-Hsiang Hsu
金雅琴
Dr. Ya-Chin King
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2000
畢業學年度: 88
語文別: 英文
論文頁數: 116
中文關鍵詞: 電性可擦拭可編碼唯讀記憶體快閃式記憶體NAND型陣列
外文關鍵詞: EEPROM, Flash Memory, NAND type array
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  • 快閃式記憶體具有當電源切掉後,仍具有記憶功能的非揮發性記憶元件,目前被運用於數位相機,mp3撥放器,與手機等需儲存大量資料的機器中。但是當資料量變得相當可觀後,元件本身的存取速度會變成影響儲存速度的關鍵因素,為了解決這種問題,本篇論文提出一種適用於NAND型快閃式記憶體陣列結構的高速編碼方法,其中應用了元件暫時儲存 (In Cell Temporary Storage,簡稱ICTS) 資料以及多重頁字元線編碼方式 (Multiple Wordline Parallel Programming,簡稱MWPP) 以加速操作。在前例中,只使用單頁編碼模式來加快操作速度。在本文中,提出大量的資料被暫時儲存在NAND型陣列快閃式記憶體之奇數或偶數字元線的元件寄生電容中,當資料全部傳入後,一併進行編碼寫入,以提供高速的寫入。操作過程第一步為閘極加電壓使得通道導通,資料就由位元線傳入並以電荷模式暫存於元件內,第二部即為閘極加一編碼電壓,利用穿隧效應將電子由通道轉移到浮動閘,就完成操作。實驗結果不僅驗證了在資料傳輸過程中,資料暫存的時間遠長於傳輸時間,並證明不會有明顯的閘極干涉現象。在元件可靠度方面,亦證明此種操作方式可以進行1E6次的編碼擦拭,並且在經過1E4次的操作後,發現儲存的資料在250C的高溫操作下不會流失,具有高度的可靠性。最後並且針對此種元件縮小後對操作的影響,發現臨界電壓的差異(寫入與抹除的差別)會變得更大,特性有變好的傾向,也就代表了元件在未來的發展空間極是可以期待的。此篇所提出的操作方式 (ICTS+MWPP) ,將會是高速編碼,高可靠性快閃是記憶體的最佳選擇。


    A fast programming scheme for NAND type architecture utilized cell storage and multiple wordline programming is dedicated in this study. In the prior arts, only multiple page programming is adopted to increase the program throughput. To obtain higher throughput, the large amount of data are stored in the even or odd cells and programmed simultaneously. Experimental results demonstrate the reliable storage characteristics and endurance characteristics (more than 1E6 cycles). Besides, the programming ability is enormously improved with the scaled device. Therefore, the proposed In Cell Temporary Storage (ICTS) and Multiple Wordline Page Programming (MWPP) is a promising candidate for high speed and high reliability applications.

    ABSTRACT II ACKNOWLEDGEMENT IV LIST OF CONTENTS V LIST OF FIGURES VII LIST OF TABLES X CHAPTER ONE INTRODUCTION 11 CHAPTER TWO REVIEW OF PRIOR APPROACHES 13 2.1 Word Line Boost Architecture 13 2.1.1 Conventional NAND type program architecture 13 2.1.2 Modified NAND type program architecture 14 2.1.3 Self boost program architecture 15 2.1.4 Local self boost program architecture 15 2.2 Temporary Storage Architecture 16 2.2.1 DRAM-NVRAM 16 2.2.2 Stacked storage capacitor 17 2.3 Page Program Architecture 18 CHAPTER THREE THEORY AND DEVICE PREPARATION 26 3.1 EEPROM Physics 26 3.1.1 Fowler-Nordheim (FN) tunneling 27 3.1.2 Capacitance coupling coefficient 28 3.1.3 Current voltage characteristics 29 3.1.4 EEPROM model 30 3.2 High Speed/Density EEPROM 31 3.2.1 Novel in cell temporary storage (ICTS) technique 31 3.2.2 Novel multiple wordline parallel programming (MWPP) technique 33 3.2.3 Operational flow 33 3.3 Experimental Design 34 3.3.1 Process flow 34 3.3.2 Test key design 36 3.3.3 Measurement environment 37 CHAPTER FOUR EXPERIMENT AND ANALYSIS 57 4.1 Parameter Extraction and Model Establishment 57 4.1.1 Equivalent cell model 57 4.1.2 Parameter extraction 58 4.1.3 Analytical equation 58 4.2 Program Characteristic 62 4.2.1 VTH related drain voltage 62 4.2.2 VTH related 1st step gate voltage (VCG1) 63 4.2.3 VTH related 2nd step gate voltage (VCG2) 64 4.2.4 VTH related passing gate voltage 64 4.2.5 VTH related initial VTH 65 4.3 Data Retention 65 4.3.1 Junction leakage 66 4.3.2 Sub-threshold leakage 67 4.4 Erase Characteristic 68 4.5 Read Characteristic 69 4.6 Reliability Issue 69 4.6.1 Endurance 70 4.6.2 Threshold distribution 70 4.6.3 Disturbance 71 4.6.4 Charge retention 73 4.7 Scaling Trend 73 4.7.1 Coupling ratio vs. threshold voltage 73 4.7.2 Scaling down 74 CHAPTER FIVE CONCLUSIONS 113 REFERENCE 114

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