在電子產品的市場趨勢逐漸朝向微小化與多功能的情況下，晶圓級封裝(Wafer Level Package)與多晶片模組(Multi-Chip Module)在目前封裝設計中被廣泛的使用；結合此兩種封裝設計概念，本研究討論一種利用類似晶圓級封裝技術方式重新沉積佈線層(Redistribution Layer)的類晶圓級多晶片模組(Quasi-Wafer Level Multi-Chip Module)，並利用有限單元分析軟體ANSYS®探討此封裝結構的熱傳特性與內埋金屬導線可靠度，指出此結構中的高分子材料是影響其散熱能力與導線結構可靠度的主要因素。在熱傳遞分析中首先針對層板結構的散熱特性進行評估，而後採用等效層板結構簡化此類晶圓級多晶片模組的模型複雜度，並對此類晶圓級多晶片模組的散熱途徑進行分析，設計能增強此封裝體散熱效益的散熱增強結構。此外，分別以二維與三維的有限單元模型進行結構分析，討論致使金屬導線部份失效的原因，並根據此原因設計出能降低導線應力集中現象的設計規範。
研究結果指出熱對流邊界是影響導線層等效合理性的主要因素，當封裝體中層板結構僅有少數邊界與空氣接觸，以體積比混合導線與高分子材料之熱傳導係數的等效方法可適用於熱傳遞有限單元分析中。在類晶圓級多晶片模組中，功率放大器(Power Amplifier)是主要的發熱晶片，將晶片與晶片載板間的黏膠材料(Adhesive)以熱擴散片(Heat Spreader)取代可以增強熱能由發熱晶片傳導至封裝體表面的能力；但由於封裝體表面的散熱能力有限，以熱導通孔(Thermal Via)建立由晶片載板至印刷電路板的散熱途徑將有助於進一步提升封裝體的散熱效能。
因為晶片、金屬導線與其周圍的介電材料(Dielectric Material)間的熱膨脹係數差異較大，晶片周圍的金屬導線在升溫負載下將產生應力集中，而與晶片連接的金屬導通孔其應力集中現象更為顯著；研究指出晶片上導通孔之位置必須避免位於晶片邊界與深入晶片內部，而在晶片內部的導通孔可利用曲線導線減少介電材料對導線與導通孔的推擠效應；此外，在與電路板組裝後的封裝結構中設計熱擴散片結構將使得晶片上應力集中現象更為明顯，而減少晶片的厚度有助於改善此現象。

The current market trend in electronic devices leans toward the use of small-sized and multi-functional devices. In particular, package design technologies like Wafer Level Package and Multi-Chip Module have been the widely used. With the combination of these two package designs, the Quasi-Wafer Level Multi-Chip Module structure which uses wafer-level technology to deposit the redistribution layer is discussed in this study. We use the finite element analysis software ANSYS® to discuss the thermal performance and embed metal line reliability. The results indicate that the polymer material in this package is the major factor which influences thermal efficiency and the embedded trace reliability in the structure. First, we probe into the thermal property of equivalent laminated structure. Then we use this equivalent structure to simplify the finite element model and carry out the finite element thermal analysis. Furthermore, we use 2D and 3D finite element models to respectively simulate the embedded trace behaviors upon thermal loading, and discuss the reasons behind metal line destruction. Finally, we design some thermal and reliability enhanced structures based on these results.
Our study’s results indicate that the convection boundary is the major factor of the equivalent trace layer’s reasonability. When the lamination layer in the package structure has only a few boundaries that contact with ambient air, the thermal conductivity of this equivalent region could be decided through mixing with its volume ratio and suit for heat transfer finite element problem. The power amplifier is the main heat source in this package, so replacing the adhesive with a heat spreader would improve the thermal performance from the chip to the package’s surface. Due to the package’s limitation on its heat convection ability, building a thermal via to create a new thermal path from the chip carrier to PCB would enhance the thermal performance of this package.
Due to the CTE mismatch among the chip, the trace and the dielectric material, the embedded metal line surrounding the chip would induce stress concentration under thermal loading, especially at via structure. The via on chip should be removed from the die edge but should not to go deep into the chip. The stress concentration on the via caused by the expansion of the dielectric material could be reduced by using curved trace. Furthermore, to create a heat spreader in the board level structure might influence seriously the reliability of the via on chip. Correspondingly, the reduction of chip thickness would improve the reliability of the via structure.

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