Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with minimum skew and latency. While there are a few related works in literature, none of them considers the reliability of TSVs. Accordingly, the failure of any TSV in the clock tree yields a bad chip. The naive solution using double-TSV can alleviate the problem. But the significant area overhead renders it less practical for large designs.
In this thesis, a novel TSV fault-tolerant unit (TFU) is proposed, which can provide tolerance against TSV failures in a 3D clock network. It makes use of the existing 2D redundant trees designed for pre-bond testing, and thus has minimum area overhead. Compared to the double TSV technique, the 3D clock network constructed by our TFUs can achieve 53% area reduction and while maintaining the yield rate. To the best of the author’s knowledge, this is the first practical work in literature that considers the fault tolerance of a 3D clock network.

在三維晶片相關的研究中，時脈樹合成的問題是最重要也最具有挑戰性的，時脈訊號在三維晶片中必須在最小的偏差與延遲的情況下，透過矽晶穿孔的結構將訊號傳遞到不同的晶片層。而在先期的研究中，與這方面相關的並不多，同時也沒有任何研究考慮到矽晶穿孔的可靠性，但是在時脈樹中任何矽晶穿孔的損壞都可能造成整顆晶片無法使用。一個簡單的解決方法是使用雙矽晶穿孔，但是這個方法可能會使用過多的晶片面積而不適用於較大規模的晶片上。
在這篇論文中，我們提出一個新的矽晶穿孔容錯設計，藉由使用堆疊三維晶片前測試用的冗餘時脈樹，來增加時脈樹對矽晶穿孔的容錯能力，因為是使用現有的結構，所以這個設計可以使用較小的面積來達成。相較於雙矽晶穿孔的方法，我們的設計可以少使用53%的面積就可以達到跟雙矽晶穿孔一樣的良率，另外，就我們所知我們的方法是第一個在三維晶片中的容錯時脈設計。

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