在先進製程中，插置電力線段是一項新的方法可以用來減緩電壓下降的情形，
藉由輕微地移動元件的位置，可以有效地提升電力線段可插置的比例，
首先，為了節省記憶體用量，我們不使用
多維度陣列而是建立出了單向無環圖快速地呈現動態規劃去用多列擺置調整優化電力線段插置，
因此記憶體用量變成原來的約萬分之一。
接著我們針對一維圖案的設計法則情形下提出建構逐步校正的動態規劃去最大化電力線段可以插置的數量。
另一方面，因為特徵尺寸持續地縮減，在現在的電路設計上汲極構造相鄰的限制成為了新興的挑戰，
為了同時地增加電力線段插置比例跟滿足汲極構造相鄰，必須想出一個能同時考慮這兩個目標的方法，
我們用元件平移、翻轉、及冗餘原極插置去修改了基於單向無環圖的動態規劃用比較小的元件位移來解決所有的汲極構造相鄰違反同時最大化可插置地電力線段數量。

Power staple insertion is a new methodology for IR drop mitigation in advanced technology nodes.
Detailed placement refinement which perturbs an initial placement slightly is an effective strategy to increase the success rate of power staple insertion.
First, we show how to construct a directed acyclic graph (DAG) on the fly efficiently to implement the dynamic program for staple insertion optimization for multi-row placement refinement in order to conserve memory usage instead of using a multi-dimensional array which incurs huge space overhead.
The memory usage can thus be reduced by a few orders of magnitude in practice.
Then, we present a correct-by-construction approach based on dynamic programming to maximize the total number of legal power staples inserted subject to the design rule for 1D patterning.
On the other hand, since the feature size continues to diminish, the drain-to-drain abutment (DDA) constraints are emerging challenges on modern circuit designs.
To increase staple insertion rate and satisfy the DDA constraints at the same time, it is necessary to formulate a methodology to consider both objectives together.
We modify the DAG-based dynamic programming to adopt cell shifting, cell flipping and dummy source node insertion to resolve all DDA violations while the total amount of valid power staples is maximized with less cell displacement.

[1] P. Besser, “BEOL interconnect innovations for improving performance,” in NCCAVS Joint
Users Group Technical Symposium, 2017.
[2] H. Chen, C.-K. Cheng, A.B. Kahng, Q. Wang and M. Wang, “Optimal planning for meshbased power distribution,” in Asia and South Pacific Design Automation Conference 2004,
pp. 444-449.
[3] S. S.-Y. Liu, C.-J. Lee, C.-C. Huang, H.-M. Chen, C.-T. Lin, and C.-H. Lee, “Effective power
network prototyping via statistical-based clustering and sequential linear programming,” in
Design, Automation Test in Europe Conference Exhibition, 2013,pp. 1701-1706.
[4] W.-H. Chang, C.-H. Lin, S.-P. Mu, L.-D. Chen, C.-H. Tsai, Y.-C. Chiu, and M. C.-T. Chao,
“Generating routing-driven power distribution networks with machine-learning technique,”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36,
no. 8, pp. 1237–1250, 2017.
[5] C.-Y. Yu, Y.-T. Hou, C.-M. Fu, W.-H. Chen, and W.-Y. Lo, “Apparatus and method
for mitigating dynamic IR voltage drop and electromigration affects,” 2017, US Patent,
US9768119B2.
[6] L. Liebmann, V. Gerousis, P. Gutwin, X. Zhu and J. Petykiewicz, “Exploiting Regularity:
breakthroughs in sub-7nm place-and-route,” in Proc. of SPIE, Design-Process-Technology
Co-optimization for Manufacturability XI, pp. 101480F1–F10, 2017.
[7] S. i. Heo, A. B. Kahng, M. Kim, L. Wang, and C. Yang, “Detailed placement for IR drop
mitigation by power staple insertion in sub-10nm VLSI,” in Proc. of the conference on
Design, Automation and Test in Europe, 2019, pp. 824–829.
[8] G. Luk-Pat, A. Miloslavsky, B. Painter, L. Lin, P. D. Bisschip and K. Lucas, “Design
Compliance for Spacer Is Dielectric (SID) Patterning,” in Proc. of SPIE, Optimal Microlithography XXV, 2012 pp. 83260D1–D13.
[9] K. Ahmed and K. Schuegarf, “Transistor wars,” in IEEE Spectrum, pp. 50-66, Nov. 2011.
[10] Y. Du and M. Wong, “Optimization of standard cell based detailed placement for 16nm
FinFET process,” in Proc. of Design, Automation, and Test in Europe Conference, 2014,
pp. 1-6.
35
REFERENCES
[11] M. Choi, V. Moroz, S. Lee, and O. Penzin, “14 nm FinFET Stress Engineering with Epitaxial SiGe Source/Drain,” in Proc. of International Silicon-Germanium Technology and
Device Meeting, 2012, pp. 1-2.
[12] K. Han, A. B. Kahng and H. Lee, “Scalable detailed placement legalization for complex sub14nm constraints,” in Proc. of IEEE/ACM International Conference on Computer Aided
Design, 2015, pp. 867-873.
[13] Y.-W. Tseng and Y.-W. Chang, “Mixed-Cell-Height Placement Considering Drain-to-Drain
Abutment,” in Proc. of IEEE/ACM International Conference on Computer Aided Design,
2018, pp. 1-6.
[14] Y. Lin, B. Yu, Y. Zou, Z. Li, C. J. Alpert, and D. Z.Pan, “Stitch Aware Detailed Placement
for Multiple E-Beam Lithography,” in Proc. of Asia and South Pacific Design Automation
Conference, 2016, pp. 186-191.
[15] Y.-X. Ding, C. Chu, and W.-K. Mak, “Pin accessibility-driven detailed placement refinement,” in Proc. of International Symposium on Physical Design, 2017, pp. 133-140.
[16] W.-K.Mak, W.-S. Kuo, S.-H. Zhang, S.-I. Lei and C. Chu, “Minimum Implant Area-Aware
Placement and Threshold Voltage Refinement,” in IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, 2017, pp. 1103-1112.
[17] C. Han, A. B. Kahng, L. Wang, and B. Xu, “Enhanced Optimal Multi-Row Detailed Placement for Neighbor Diffusion Effect Mitigation in Sub-10 nm VLSI,” in IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems, 2018, pp. 1703–1716.
[18] Arm Developer, https://developer.arm.com/.
[19] OpenCores, Open Source IP-Cores, http://www.opencores.org.
[20] NanGate FreePDK15 Open Cell Library https://si2.org/open-cell-library.
[21] “ISPD 2015 Blockage-Aware Detailed Routing-Driven Placement Contest, ”https://
www.ispd.cc/contests/15/web/benchmark.html.