本篇論文提出了一個管線化序列產生器架構採用多工正反器，以達到高輸出效率及低成本的序列傳輸界面發送端解決方式。一個多工暫存器是同時具備組合電路的邏輯功能及時序電路的儲存功能的電路。多工正反器即為多級串接的暫存器和多功暫存器。採用多工正反器於序列化時，可以省去許多當作時序電路的暫存器的使用，藉由減少邏輯閘數，達到節省能量消耗、晶片面積以及設計複雜度的目標。由於輸出級採用與傳統架構相同之多工器，使得速度的瓶頸電路維持在最高速的輸出級，而前面被多工正反器取代的低速級則不影響整體系統操作速度。分析及模擬結果顯示，採用新推出的序列產生器架構可以減少百分之五十二的邏輯閘數，並且不會降低操作速度。為了驗證新推出的序列產生器架構的功能是否正確，製作了兩顆晶片。分別是四對一多工正反器以及八對一序列產生器採用新推出的架構。兩顆晶片皆採用台積電九零奈米互補式金屬氧化物半導體製程，由國家晶片系統設計中心提供製程資料及晶片下線服務。量測結果顯示，多工正反器可操作在每秒六十億筆資料的速度，並且無資料錯誤（錯誤率小於一千億分之一）。而採用包含多工正反器的新架構的序列產生器可操作在每秒一百二十億筆資料的速度，並且無資料錯誤（錯誤率小於一千億分之一）。

This paper proposes a pipelined serializer topology with MUX-FFs to be a high-throughput and low-cost solution for serial link interface transmitters. Analysis and simulation results show that the serializer in proposed topology reduces 52% the gate count without slowing down the serializer. To verify the functions of the proposed design, two chips are implemented with the 4-to-1 MUX-FF and proposed 8-to-1 serializer in 90 nm CMOS technology. The measured results shows that the MUX-FF and the proposed serializer with MUX-FFs are bit-error-free (with BER < 10^-12), operate at up to 6 Gbits/s and 12 Gbit/s, respectively.

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