在同步電路設計中，時脈偏移的最小化是非常困難的，因為在單一的時鐘樹下需要滿足多個不同的限制，而限制是發生在複雜的電壓模式環境下，會有特定的模組運作在不同的電壓下。在本篇論文中，我們主要利用可調變延遲緩衝器的，可調變延遲的特性，在不同的電壓模式下，最小化時脈偏移。假設已經擺放固定個數和位置的可調變延遲緩衝器，我們提出了一個線性計算時間最佳化演算法，可以決定每個可調變延遲緩衝器的數值，使得在利用可調變延遲緩衝器做調整下，時脈偏移的結果會最佳化。並且我們提出了一個有效率探索的方法，決定好的位置來擺放這些可調變延遲緩衝器。我們實驗結果顯示出有意義的改進相較於沒使用這些可調變延遲緩衝器。

In synchronous circuit designs, clock skew is difficult to minimize because a single physical layout of a clock tree must satisfy multiple constraints in a complicated power mode environment where certain modules may operate with different voltages. In this paper, we use Adjustable Delay Buffers (ADB) whose delays can be tuned or adjusted to minimize clock skew under different power modes. Assuming that the positions of k ADBs are already determined, we propose a linear-time optimal algorithm which assigns the values of ADBs so that the skew is optimal among all possible ADB assignments. We also propose an efficient heuristic to determine good positions for ADBs. Our results show significant improvement when compared to cases without ADBs.

[1] C. J. Alpert, A. Devgan, and S. T. Quay, “Buffer insertion with accurate gate and interconnect delay computation,” in Proc. of IEEE/ACM Design Automation Conference., pp. 479–484. 1999.
[2] K. D. Boese and A. B. Kahng, “Zero-skew clock routing trees with minimum wire length,” in Proc. of 5th IEEE Int. Conf. ASIC, pp. 17–21. 1992.
[3] T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese, and A. B. Kahng, “Zero skew clock net routing,” IEEE Trans. Circuits Syst. II, vol. 39, no. 11, pp. 799–814, Nov. 1992.
[4] J. Cong, Z. Pan, L. He, C.-K. Koh, and K.-Y. Khoo, “Interconnect design for deep submicron ICs,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 478–485. 1997.
[5] J. Cong, C. Koh, and K. Leung, “Simultaneous buffer and wire sizing for performance and power optimization,” in Proc. of Int. Symposium on Low Power Electron. Design, pp. 271–276, 1996.
[6] C. C. N. Chu and D. F. Wong, “An efficient and optimal algorithm for simultaneous buffer and wire sizing,” IEEE Trans. Computer-Aided Design, vol. 18, pp. 1297-1304, Sept. 1999.
[7] Shiyan Hu , Jiang Hu, “Unified adaptivity optimization of clock and logic signals,” in Proc. of the IEEE/ACM international conference on Computer-aided design, November 05-08, 2007.
[8] N. A. Kurd, J. S. Barkatullah, R. O. Dizon, T. D. Fletcher, and P. D. Madland, “A multigigahertz clocking scheme for Pentium 4 Microprocessor,” IEEE J. Solid-State Circuits, vol. 36, pp. 1647–1653, Nov. 2001.
[9] Vishal Khandelwal and Ankur Srivastava, “Variability-Driven Formulation for Simultaneous Gate Sizing and Post-Silicon Tunability Allocation,” in Proc. of Int. Symposium on Physical design, pp. 11-18, 2007.
[10] R. Kay, G. Bucheuv, and L. T. Pileggi, “EWA: Exact wiring-sizing algorithm,” in Proc. of Int. Symposium on Physical Design, pp. 178–185, 1997.
[11] I.-M Liu, T.-L Chou, A. Aziz, and D. F. Wong, “Zero-skew clock tree construction by simultaneous routing, wire sizing, and buffer insertion,” in Proc. of Int. Symposium on Physical Design, pp. 33–38, 2000.
[12] Patrick Mahoney, Eric Fetzer, Bruce Doyle, and Sam Naffziger. ”Clock distribution on a dual-core multi-threaded Itanium-family processor,” in Digest of technical papers of the international solid-state circuits conference, 2005.
[13] T. Okamoto and J. Cong, “Buffered Steiner tree construction with wire sizing for interconnect layout optimization,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 44–49, 1996.
[14] A. Rajaram and David Z. Pan, “Robust chip-level clock tree synthesis for SOC designs”, in Proc. of IEEE/ACM Design Automation Conference, pp.720-723, June 2008
[15] S. S. Sapatnekar, “RC Interconnect optimization under the Elmore delay model,” in Proc. of IEEE/ACM Design Automation Conference, pp. 387–391, 1994.
[16] Simon Tam, Stefan Rusu, Utpal Nagarji Desai, Robert Kim, Ji Zhang, and Ian Young. ”Clock generation and distribution for the first IA-64 microprocessor,” IEEE Journal of Solid-State Circuits, pages 35(11):1545–1552, Nov 2000.
[17] Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen, “Zero skew clock tree optimization with buffer insertion/sizing and wire sizing,” IEEE Transactions on CAD, Vol. 23, No. 4, Jun. 2004.
[18] J.-L. Tsai, L. Zhang, C. Chen, “Statistical timing analysis driven post-silicon-tunable clock-tree synthesis,” in Proc. of Int. Conf. on Computer-Aided Design, pp. 575-581, Nov. 2005.
[19] E. Takahashi, Y. Kasai, M. Murakawa, and T. Higuchi, “A post-silicon clock timing adjustment using genetic algorithms,” in Digest of technical papers of the symp. on VLSI circuits, pages 13–16, 2003.
[20] Jeng-Liang Tsai, DongHyun Baik, Charlie Chung-Ping Chen, and Kewal K. Saluja. “A yield Improvement methodology using pre- and post-silicon statistical clock scheduling,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pages 611–618, 2004.
[21] Kai Wang; Ran, Y.; Hailin Jiang; Marek-Sadowska, M., "General skew constrained clock network sizing based on sequential linear programming," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.24, no.5, pp. 773-782, May 2005