本實驗成功的製作了金屬(Al)/氧化鉿(HfO2)/半導體(p-Si)與金屬(Al)/氧化鈰(CeO2)/半導體(p-Si)兩種結構的電容器、n 通道場效電晶體。探討在不同型態電流應力下崩潰電荷的可靠度特性，同時利用閘控二極體的技術探討使用氧化鈰與氧化鉿/氧化鈰堆疊結構為閘極絕緣層的介面特性。針對9.12 nm, 8.2 nm與6.51 nm不同厚度下的氧化鉿薄膜，施加定電流應力，分別萃取出的韋布斜率為3.42, 2.90與1.83。針對不同的指數0.6與1，可以藉由細胞基礎分析模型得到氧化鉿薄膜的缺陷密度分別為0.97nm與1.63nm。針對厚度為9.12 nm的氧化鉿薄膜，使用傳輸線脈衝波應力測試，得到的韋布斜率約為3.86。使用傳輸線脈衝波應力所得到的崩潰電荷值比起由定電流應力下得到的約小上5個數量級。然而，我們利用電洞產生係數分析發現，傳輸線脈衝波應力下的係數比起定電流應力下的約大上4個數量級。因此我們可以定量的解釋兩種應力下崩潰電荷值的差距。
使用次臨界斜率萃取得氧化鈰與氧化鉿/氧化鈰堆疊結構為閘極絕緣層的介面缺陷密度分別為1.47×1012 cm-2 eV-1和1.53×1012 cm-2 eV-1。藉由閘控二極體與次臨界斜率得到氧化鈰與氧化鉿/氧化鈰堆疊結構在高介電薄膜與矽基板處的等效捕陷截面積分別為8.68×10-15 cm2 和4.83×10-15 cm2。

Metal-insulator-semiconductor (MIS) capacitors and n-channel field effect transistors with HfO2 and CeO2 gate dielectrics were successfully fabricated. The reliability properties such as charge-to-breakdown (QBD) with different types of current stress were characterized. The high-k/Si interface properties with CeO2 and HfO2/CeO2 laminated gate oxides were investigated by the gated-diode technique. The Weibull slope and the defect size of HfO2 gate dielectric were determined. The extracted Weibull slope (β) from constant current stress (CCS) measurement for different thicknesses of 9.12 nm, 8.2 nm and 6.51 nm are found to be 3.42, 2.90 and 1.83, respectively. The defect size a0 extracted by the cell-based analytic model with different exponents of 0.6 and 1 are 0.97 nm and 1.63 nm, respectively. The extracted Weibull slope (β) from transmission line pulsing (TLP) measurement for thickness of 9.12 nm is about 3.86. The QBD values extracted from the TLP method are about 5 order of magnitude smaller than those extracted from the CCS method. However, the hole generation coefficient extracted from the TLP method is about 4 order of magnitude larger than that extracted from the CCS method. Hence, this can quantitatively explain the difference of QBD between the CCS method and the TLP method.
The interface trap density (D¬it) of CeO2 and HfO2/CeO2 laminated gate dielectrics determined by the subthreshold swing method are 1.47×1012 cm-2 eV-1 and 1.53×1012 cm-2 eV-1, respectively. The effective capture cross section of surface state (σs) of CeO2 and HfO2/CeO2 laminated gate oxides extracted using the gated diode technique and the subthreshold swing measurement were about 8.68×10-15 cm2 and 4.83×10-15 cm2, respectively.

[1] H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Makamura, M. Saito, and H. Iwai, “1.5 nm direct-tunneling gate oxide Si MOSFET’s,” IEEE Trans. Electron Devices, vol. 43, pp. 1233-1241, 1996.
[2] J. L. Autran, R. Devine, C. Chaneliere, and B. Balland, “Fabrication and characterization of Si-MOSFET’s with PECVD amorphous Ta2O5 gate insulator,” IEEE Electron Device Lett., vol. 18, pp. 447-449, 1997.
[3] C. Chaneliere, S. Four, J. L. Autran, R. A. B. Devine, and N. P. Sandler, “Properties of amorphous and crystalline Ta2O5 thin films deposited on Si from Ta(OC2H5)5 precursor,” J. Appl. Phys., vol. 83, no. 9, pp. 4823-4829, 1998.
[4] Q. Lu, D. Park, A. Kalnitsky, C. Chang, C. C. Cheng, S. P. Tay, T. J. King, and C. Hu, “Leakage Current Comparison Between Ultra-Thin Ta2O5 Films and Conventional Gate Dielectrics,” IEEE Electron Device Lett., vol. 19, no. 9, pp. 341-342, 1998.
[5] D. Park, Y. King, Q. Lu, T. J. King, C. Hu, A. Kalnitsky, S. P. Tay, and C. C. Cheng, “Transistor Characterization with Ta2O5 Gate Dielectric,” IEEE Electron Device Lett., vol. 19, no. 11, pp. 441-443, 1998.
[6] B. C. Lai, N. Kung, and J. Y. Lee, “A study on the capacitance-voltage characteristics of metal-Ta2O5-silicon capacitors for very large scale integration metal-oxide-semiconductor gate oxide applications,” J. Appl. Phys., vol. 85, no. 8, pp. 4087-4090, 1999.
[7] J. C. Yu, B. C. Lai, and J. Y. Lee, “Fabrication and Characterization of Metal-Oxide-Semiconductor Field-Effect Transistors and Gated Diodes Using Ta2O5 Gate Oxide,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 537-539, 2000.
[8] B. C. Lai, J. C. Yu, and J. Y. Lee, “Ta2O5/Silicon Barrier Height Measured from MOSFETs Fabrication with Ta2O5 Gated Dielectric,” IEEE Electron Device Lett., vol. 22, no. 5, pp. 221-223, 2001.
[9] J. Y. Lee and B. C. Lai, Ferroelectric and dielectric thin films, edited by H. S. Nalwa, New York: Academic press, 2001.
[10] A. I. Kingon, J. P. Maria, and S. K. Streiffer, “Alternative dielectrics to silicon dioxide for memory and logic devices,” Nature, vol. 406, no. 6799, pp.1032-1039, 2000.
[11] K. Karakaya, B. Barcones, Z. M. Rittersma, J. G. M. van Berkum, M. A. Verheijen, G. Rijnders, and D. H. A. Blank, “Electrical and structural characterization of PLD grown CeO2-HfO2 laminated high-k gate dielectrics,” Mater. Sci. in semiconductor processing, vol. 9, pp.1061-1064, 2006.
[12] Y. Nishikawa, T. Yamaguchi, M. Yoshiki, H. Satake, and N. Fukushima, “Interfacial properties of single-crystalline CeO2 high-k gate dielectrics directly grown on Si (111),” Appl. Phys. Lett., vol. 81, no. 23, pp.4386-4388, 2002.
[13] R. E. Nieh, C. S. Kang, H. J. Cho, K. Onishi, R. Choi, S. Krishnan, J. H. Han, Y. H. Kim, M. S. Akbar, and J. C. Lee, “Electrical Characterization and Material Evaluation of Zirconium Oxynitride Gate Dielectric in TaN-gated NMOSFETs With High-Temperature Forming Gas Annealing,” IEEE Trans. Electron Devices, vol. 50, no. 2, pp. 333-340, 2003
[14] D. Park, Y. King, Q. Lu, T. J. King, C. Hu, A. Kalnitsky, S. P. Tay, and C. C. Cheng, “Transistor characterization with Ta2O5 gate dielectric,” IEEE Electron Device Lett., vol. 19, no. 11, pp. 441-443, 1998.
[15] B. K. Park, J. Park, M. Cho, C. S. Hwang, K. Oh, Y. Han, and D. Y. Yang, “Interfacial reaction between chemically vapor-deposited HfO2 thin films and a HF-cleaned Si substrate during film growth and postannealing,” Appl. Phys. Lett., vol. 80, no. 13, pp. 2368-2371, 2002.
[16] Iwai, H. Ohmi, S. Akama, S. Ohshima, C. Kikuchi, A. Kashiwagi, I. Taguchi, J. Yamamoto, H. Tonotani, J. Kim, Y. Ueda, I. Kuriyama, and A. Yoshihara, “Advanced gate dielectric materials for sub-100 nm CMOS,” in IEDM Tech. Dig., pp.625-628, 2002.
[17] M. Gutowski, J. E. Jaffe, C. L. Liu, M. Stoker, R. I. Hegde, R. S. Rai, and P. J. Tobin, “Thermodynamic stability of high-k dielectric metal oxide ZrO2 and HfO2 in contact with Si and SiO2,” Appl. Phys. Lett., vol. 80, no. 11, pp. 1897-1899, 2002.
[18] K. J. Hubbard and D. G. Schlom, “Thermodynamic stability of binary oxides in contact with silicon,” J. Mater. Res., vol. 11, no. 11, pp. 2757-2776, 1996.
[19] Z. J. Luo and T. P. Ma, “Ultra-thin ZrO2 (or silicate) with high thermal stability for CMOS gate application,” Symp. VLSI Tech. Dig., PP.135-136, 2001.
[20] Y. Kim, G. Gebara, M. Frelier, J. Barnett, D. Riley, J. Chen, K. Torres, J. E. Lim, B. Foran, F. Shappur, A. Agarwal, P. Lysaght, G. A. Brown, C. Young, S. Borthakur, H. J. Li, B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R. Bergmann, R. W. Murto, A. Hou, H. R. Huff, E. Shero, C. Pomarede, M. Givans, M. Mazanez, and C. Werkhoven, “Conventional n-channel MOSFET device using single layer HfO2 and ZrO2 as high-k gate dielectrics with polysilicon gate electrode,” IEDM Tech. Dig.,2001, pp. 455-458.
[21] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “Hafnium and zirconium silicates for advance gate dielectrics,” J. Appl. Phys., vol. 87, no. 1, pp. 484-492, 2000.
[22] L. Kang, B. H. Lee, W. J. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi, and J. C. Lee, “Electrical characteristics of highly reliable ultrathin hafnium oxide gate dielectric,” IEEE Electron Device Lett., vol. 21, no. 4, pp. 181-183, 2000.
[23] S. M. Sze, Physics of semiconductor device, 2nd ed., Wiley, New York, 1981.
[24] C. H. Lee, H. F. Luan, W. P. Bai, S. J. Lee, T. S. Jeon, Y. Senzaki, D. Roberts, and D. L. Kwong, “MOS characteristics of ultra thin rapid thermal CVD ZrO2 and Zr silicate gate dielectrics,” IEDM Tech. Dig., 2000,pp. 27-30.
[25] J. R. Yeargan, H. L. Taylor, “The Poole-Frenkel effect with compensation present,” J. Appl. Phys. vol. 39, no. 12, pp. 5600-5604, 1968.
[26] D. K. Schroder, Semiconductor Material and Device Characteristics, Arizona: Wiley press, 1998.
[27] M. Depas, T. Nigam, and M. M. Heyns, “Soft breakdown of ultra thin gate oxide layers,” IEEE Trans. Electron Devices, vol. 43, no. 9, pp. 1499-1503, 1996.
[28] E. Rosenbaum, J. C. King, and C-M Hu, “Accelerated testing of SiO2 reliability,” IEEE Trans. Electron Devices, vol. 43, no. 1, pp. 70-80, 1996.
[29] http://experts.about.com/e/w/wa/Waloddi_Weibull.htm
[30] Y. H. Kim, K. Onishi, C. S. Kang, H. J. Cho, R. Nieh, S. Gopalan, R. Choi, J. Han, S.Krishnan, and J. C. Lee, ”Area dependence of TDDB characteristics for HfO2 gate dielectrics,” IEEE Electron Device Lett., vol. 23, no. 10, pp. 594-569, 2002.
[31] T. Nigam, R. Degraeve, G. Groeseneken, M. M. Heyns, and H. E. Maes, “Constant current charge-to-breakdown: Still a valid tool to study the reliability of MOS structures? ,” in Proc. IRPS, pp. 62-69, 1998.
[32] T. Nigam, R. Degraeve, G. Groeseneken, M. M. Heyns, and H. E. Maes, “Constant current charge-to-breakdown: Still a valid tool to study the reliability of MOS structures?,” in Proc. IRPS, pp. 62-69, 1998.
[33] R. Degraeve, G. Groeseneken, R. Bellens, J. L. Ogier, M. Depas, P. J. Roussel, and H. E. Maes, “New insights in the relation between electron trap generation and the statistical properties of oxide breakdown,” IEEE Trans. Electron Devices, vol. 45, pp. 904-911, 1998.
[34] R. J. Carter, E. Cartier, M. Caymax, S. De Gendt, R. Degraeve, G. Groeseneken, M. Henyns, T. Kauerauf, A. Kerber, S. Kubicek, G. Lujan, L. Pantisano, W. Tsai, E. Yong, “Electrical characterization of high-k materials prepared by atomic layer CVD,” IEEE Int. Workshop on Gate Insulator, pp. 94-99, 2001.
[35] I. C. Chen, S. Holland, and C. Hu, “A quantitative model for time-dependent breakdown in SiO2,” in Proc. IRPS, vol. 23, pp. 24-27, 1985.
[36] J. Lee, I. C, Chen, and C. Hu, “Statistical modeling of silicon dioxide reliability,” in Proc. IRPS, vol. 26, pp. 131-138, 1988.
[37] D. Crook, “Method of determining reliability screens for time dependent dielectric breakdown,” in Proc. IRPS, vol. 17, pp. 1-4, 1979.
[38] E. S. Anolick, G. Nelson, “Low field time dependent dielectric integrity,” in Proc. IRPS, vol. 7, pp. 8-12, 1979.
[39] J. W. Mcpherson and D. A. Baglee, “Acceleration parameters for thin gate oxide stressing,” in Proc. IRPS, vol. 23, pp. 1-4, 1985.

[40]Jordi Sune, “New physics-based analytic approach to the thin-oxide breakdown statistics,” IEEE Electron Device Lett., vol. 22, no. 6, pp. 296-298, 2001.
[41] J. H. Stathis, “Percolation models for gate oxide breakdown,” J. Appl. Phys., vol. 86, no. 10, pp. 5757-5766, 1999.
[42] J. P. Chang and Y.-S. Lin, “Dielectric Property and Conduction Mechanism of Ultrathin Zirconium Oxide Films,” Appl. Phys. Lett., vol. 79, no. 22, p .3666, 2001.
[43] S. G. Sun and J. D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxided silicon surfaces,” IEEE Transaction on Electron Devices, 27, p. 1497, 1980
[44] Y. Taur and T. H. Ning , Fundamentals of Modern VLSI Devices, 1st ed. (Cambridge, 1998)
[45] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration”, IEEE Transaction on Electron Devices, 41, p. 2357, 1994
[46] Sorin Cristoloveanu, Hisham Haddara, and Nathalie Revil, “Defect
Localization Induced by Hot Carrier Injection in Short Channel
MOSFETs: Concept, Modeling, and Characterization,” Microelectro.
Reliab. , vol. 33, no. 9, p. 1365, 1993.
[47]A. S. Grove and D. J. Fitzgerald, “Surface Effects on p-n Junctions:
Characteristics of Surface Space-Charge Regions Under non-Equilibrium Conditions ,” Solid-Electronics Pergamon press, vol. 9, p. 783, 1966.
[48] P. U. Calzolari And S. Graffi, “A Theoretical Investigation on The
Gernation Current In Silicon p-n Junctions Under Reverse Bias,”
Solid-State Electronics, vol.15, p. 1003, 1972.
[49] T. Giebel and K. Goser, “Hot-Carrier Degradation of n-Channel
MOSFET’s Characterized by a Gated-Diode Measurement Technique,”IEEE Electron Device Lett., vol. 10, no. 2, p. 76, 1989.
[50] K. Chen, H. C. Wann, J. Dunster, P. K. Ko, C. Hu, “MOSFET Carrier Mobility Model Based on Gate Oxide Thickness, Threshold Voltage and Gate Voltages,” Solid-State Electronics vol. 39, no. 10, pp. 1515-1518, 1996.