利用備用邏輯單元完成工程變更｜國立清華大學博碩士論文庫

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研究生：	林敬倫 Jing-Lun Lin
論文名稱：	利用備用邏輯單元完成工程變更 Engineering Change Using Spare Cells
指導教授：	張世杰 Shih-Chieh Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	26
中文關鍵詞：	工程變更、備用邏輯
外文關鍵詞：	Engineering change, spare cells
相關次數：	點閱：2 下載：0
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在超大型積體電路設計流程中，由於新的設計規格、設計錯誤，或是違反設計限制等因素，需要對這個電路設計做進一步的修改，稱之為工程變更。幫助完成工程變更，一個常見的作法，是在電路中加入備用邏輯單元。因為備用邏輯單元是在設計之初就已經加入在電路之中。因此在使用備用邏輯單元來完成工程變更時，會有一些限制與考量。為了解決使用備用邏輯單元時，所面臨備用邏輯數量上的限制與考量。在這篇論文當中，我們提出了一個方法，可以循序產生多組不同的單元映對。此外，還考量備用邏輯單元使用上的彈性。以及在考量使用上的彈性的情形下，有沒有滿足備用邏輯單元在數量上的限制。我們的實驗結果顯示出，我們的方法可以使得百分之七十三的單元映對滿足備用邏輯在數量上的限制。

In the VLSI design process, the design change happens often due to new specifications or design constraint violations. This correction process for the new specification is known as engineering change (EC). Practically, the EC problem is usually resolved by using spare cells, which are inserted into the unused spaces of a chip. Because the spare cells are pre-placed, the usage of spare cells for EC is limited. In this thesis, we propose an iterative way to generate mappings of EC equations satisfying the quantity constraint of spare cells. On average, our method can generate up to 73% of mappings that are satisfy the quantity constraint.

List of Contents:

Abstract    i
Contents    ii
List of Figures    iii
List of Tables    iv
Chapter 1 Introduction    1
Chapter 2 Mapping with Spare Cells    7
2.1. Mapping Generation    8
2.2. Quantity Constraint Checking Considering Constant Insertion    13
Chapter 3 Overall Flow    17
Chapter 4 Experimental Results    20
Chapter 5 Conclusions    24
References    26

List of Figures:
Figure 1: A chip layout with spare cells……………….…………………………2
Figure 2: Flow of EC design with spare cells……………………………………3
Figure 3: Two mappings of Out = (a*b)’*(c+d)…………………………………4
Figure 4: Available spare cells for ECs ………………………………………… 5
Figure 5: Example of DAG covering ……………………………………………9
Figure 6: A mapping (one of the match selections)………………………………9
Figure 7: Constant insertion for AOI21…………………………………………13
Figure 8: Flow network modeling of quantity constraint checking …………… 15
Figure 9: Flow of quantity constraint checking…………………………………16
Figure 10: The flow of proposed methods………………………………………18
Figure 11: Overall flow of proposed methods……………………………… … 19

List of Tables:
Table 1: Experimental results of the percentages of mappings satisfy quantity constraint…………………………………………………………23

                                

[1]. C.-C. Lin, K-C Chen, and M. Marek-Sadowska, “Logic Synthesis for Engineering Change,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 3, pp. 282-292, Mar. 1999.
[2]. Y. Wantanabe and R. K. Brayton, “Incremental Synthesis for Engineering Changes,” in Proceedings of IEEE International Conference Computer Design, pp. 40-43, Oct 1991.
[3]. S.P. Khatri, A. Narayan, S.C Krishnan., K.L. McMillan, R.K. Brayton, and A. Sangi, “Engineering Change in a Non-deterministic FSM Setting,” in Proceedings of IEEE/ACM Design Automation Conference, pp. 451-456, June 1996.
[4]. F. Koushanfar, Jennifer L. Wong, Jessica Feng, and M. Potkonjak, “ILP-Based Engineering Change,” in Proceedings of IEEE/ACM Design Automation Conference, pp. 910-915, June 2002.
[5]. C.H. Lin, Y.C. Huang, S.C. Chang, and W.-B Jone, “Design and Design Automation of Rectification Logic for Engineering Change,” in Proceedings of Asia and South Pacific Design Automation Conference, pp. 1006-1009, Jan. 2005.
[6]. “Problem 5 Spare Cells Selection for Functional Change,” in 2004 IC/CAD Contest, Jan. 2004.

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