簡易檢索 / 詳目顯示

回結果列表
研究生： 林奕緯
Lin, Yi-Wei
論文名稱： 採用三倍頻耦合環振盪器建立的謝爾賓斯基碎形時脈分佈
Sierpinski Fractal Structured Clock Distribution Using Multiply-by-3 Coupled Ring Oscillators
指導教授： 徐碩鴻
Hsu, Shuo-Hung
口試委員: 黃錫瑜
Huang, Shi-Yu
謝秉璇
Hsieh, Ping-Hsuan
王廷基
Wang, Ting-Chi
許世玄
Sheu, Shyh-Shyuan
黃世旭
Huang, Shih-Hsu
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年： 2017
畢業學年度： 106
語文別： 英文
論文頁數： 140
中文關鍵詞： 時脈分佈 、謝爾賓斯基三角形 、空間填補樹 、耦合環振盪器 、注入鎖相 、Adler注入鎖相方程 、堆疊3D變壓器 、諧波萃取 、帶通濾波器 、時脈抖動轉移函數
外文關鍵詞： Clock distribution, Sierpinski triangle fractal, space-filling tree, coupled ring oscillators, injection-locking, Adler equation, stacked 3D transformer, harmonic extraction, bandpass filter, jitter transfer function
相關次數： 點閱：4  下載：0 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 本論文主要是時脈分佈網絡的研究，時脈分佈網絡的重要性和維持同步數位電路設計的運作正確性相輔相倚。因為時脈分佈就要是設計一個可以低時序不確定性又可以維持在一定程度低功耗的網絡來提供散佈在晶片各地的數位電路一個共同的時序動作參考標準。
    受到惠更斯同步實驗和相互注入鎖相研究的啟發，可以作為多時脈源分佈網路的振盪器陣列相繼被提出來。本論文進而提出以謝爾賓斯基三角形為耦合網絡的三倍頻耦合環振盪器陣列和空間填補時脈樹，並且探討這個新時脈網路分佈網絡設計帶來的優點，最重要的是探討這樣的多時脈源設計典範，在將來的多核多工處理器和先進封裝技術帶動的趨勢下如何能延續、維持同步數位電路設計的運作正確性和可測性。

    Nevertheless, the ever-growing demand for functionality and higher performance requires microprocessor with more cores and system-on-a-chip (SoC) with more functional blocks to be packed and connected. Prevalence of high latency paths appears to be increasing with chip size and circuit complexity. Clock skew and jitter are proportional to latency, and conventional buffered clock trees at GHz range has become increasingly difficult and time-consuming to meet timing uncertainty budget under 10% of the clock cycle. In high performance systems, the clock network itself consumes up to 70 % of the total chip power consumption. With the advent of IC packaging technologies such as 2.5/3D IC, design goals of both low timing uncertainties and power consumption remain, and testability turns into the new design challenge in clock distribution.
    A space filling clock tree using fractal-coupled ring oscillators has the potential to achieve the goals and challenge. The proposed scheme takes advantage of LC resonant clocking, to obtain a low-power uniform phase and amplitude multiply-by-3 clock from a unique Sierpinski-coupled ring oscillator (SCRO) array. The 3-stage interleaved SCROs resemble the Sierpinski triangle, and SCROs are synchronized with a common frequency to all. None of the previous implementations of coupled ring oscillator array uses the topology of Sierpinski triangle to couple the oscillators. A distinctive property of SCRO is that it provides an aligned output phase relationship to reduce skew. Skew in SCROs is simply removed if symmetry is maintained, which perform in the same way that H-trees do. The benefits of adopting in-phase coupled ring oscillator array in low skew clock network design include low manufacturing cost, stable performance, and easy to integrate with digital circuits.
    The Sierpinski triangle clock grid is filled by a space-filling clock tree, and the unified single-phase clock tree is built on top of SCROs for extracting the harmonics clocks. Low jitter and low power consumption is enabled by the harmonic extraction method using coupled resonators. Stacked transformers at the tree endpoints extract the 3rd harmonic of the SCRO array oscillation and scale the voltage amplitude of the extracted clock. The transformers also perform a built-in bandpass filtering function to remove injected noise and improve jitter performance. Frequency tripling and energy recycling in the 3rd harmonic clocks significantly reduce clock power consumption.
    3D IC testability is not compromised, since operation frequency of an oscillator and array clock can be determined under pre-bond test. While intra-chip and inter-chip magnetically coupling pulls oscillators to be injection-locked to a common frequency, oscillators can all start operating in harmony with one another for post-bond testing and operations. 3D coupled oscillator array clock is nevertheless an embodiment of Huygens synchronization. A test vehicle integrated in conventional TSMC 90-nm CMOS is conceptually adopted to verify and demonstrate the idea above. The measurement results already reveal substantial improvements in both power and timing uncertainty (skew and jitter).

    ABSTRACT I TABLE OF CONTENTS V LIST OF FIGURES IX LIST OF TABLE XIII CHAPTER 1. INTRODUCTION 1 1.1. MOTIVATION 1 1.2. THESIS OVERVIEW 4 CHAPTER 2. OVERVIEW OF CLOCK DISTRIBUTIONS 5 2.1. THE ROLE OF CLOCK IN SYNCHRONOUS SYSTEMS 6 2.1.1. Propagation Delay and Transition Time 7 2.1.2. Setup Time Constraint 7 2.1.3. Hold Time Constraint 8 2.2. EXAMPLES OF SEQUENTIAL LOGIC DESIGN 8 2.3. FIGURES OF MERIT FOR A CLOCK DISTRIBUTION 11 2.3.1. Timing Uncertainty 11 2.3.1.1. Clock Skew 11 2.3.1.2. Clock Jitter 12 2.3.1.3. Sources of Skew and Jitter 12 2.3.2. Clock Power 13 2.4. CONVENTIONAL CLOCK DISTRIBUTIONS 13 2.4.1. Clock distribution hierarchy 15 2.4.1.1. Global 16 2.4.1.2. Regional 16 2.4.1.3. Local 19 2.5. TREND IN RECENT METHODS 19 2.5.1. Optimized H-trees 20 2.5.2. A resonant tree-driven clock grid 21 2.5.3. Coupled oscillator arrays 23 2.5.3.1. Rotary Oscillator Array (ROA) 25 2.5.3.2. Standing wave oscillator array 27 2.5.3.3. Inductor-based resonant global clock distribution 31 2.5.3.4. Coupled ring oscillator array 33 2.6. SUMMARY 34 CHAPTER 3. RING OSCILLATOR ARRAY CLOCK 36 3.1. INTEGRATED OSCILLATORS 36 3.1.1. Oscillator Principles 36 3.1.2. Most Common Types of Integrated Oscillators 38 3.1.2.1. LC Oscillators 38 3.1.2.2. Ring Oscillators 40 3.1.3. Phase Noise 41 3.2. INJECTION LOCKING 42 3.2.1. Huygens Synchronization of Two Clocks 42 3.2.2. Generalized Adler Equation 43 3.2.3. Modeling LC Oscillator under Injection with Hard Limiters 45 3.2.4. Noise Performance of Coupled Oscillators 52 3.3. RING OSCILLATOR ARRAY CLOCKS 53 3.3.1. Cyclic-Coupled Ring Oscillator 54 3.3.2. Fractal-Coupled Ring Oscillator 59 3.4. SUMMARY 65 CHAPTER 4. SPACE-FILLING CLOCK TREE 67 4.1. MULTIPLY-BY-3 SPACE-FILLING CLOCK TREE 67 4.1.1. Extraction of 3rd Harmonic 67 4.2. USING 3D STACKED TRANSFORMER AS VLSI FILTER 69 4.2.1. Tank Resonance on XFMR Primary Winding 70 4.2.2. Bandpass Filtering on XFMR Secondary Winding 73 4.2.2.1. Concept of Bandpass Filtering 74 4.2.2.2. The T-Equivalent Circuits for Modeling Transformer 75 4.2.2.3. Transformer: A Second-Order Bandpass Filter 78 4.2.2.4. Limitations of Cascaded (Bandpass) Filter Approximation 81 4.2.2.5. Design of 3D Stacked Transformer 84 4.2.2.6. Jitter Transfer Function 87 4.3. RING OSCILLATOR DESIGN 92 4.4. SIMULATED RESULTS 94 4.5. CONSIDERATIONS OF PRACTICAL IMPLEMENTATION 97 4.6. SUMMARY 98 CHAPTER 5. EXPERIMENT 100 5.1. EXPERIMENT 100 5.1.1. Jitter 103 5.1.2. Skew 106 5.1.3. Practical Testing Consideration 107 5.2. SUMMARY 108 CHAPTER 6. CONCLUSION 110 6.1. SUMMARY 110 6.2. RECOMMENDATIONS FOR FUTURE WORK 112 6.2.1. Issues for Developing into a Practical Clock Network 113 6.2.1.1. Balanced Clock Loading 113 6.2.1.2. Clock Frequency Tuning 113 6.2.2. Monolithic 3D Integration 115 6.2.2.1. Pre-Bond Testability and Post-Bond Operability 116 6.2.2.2. 3D Clock Distribution Using Inductively Coupled Interconnect 117 6.2.2.3. Chip/Interposer Co-design of Global Clock Distribution for 3D IC 122 REFERENCES 127 LIST OF PUBLICATIONS 140

    [1] P. J. Restle et al., "A clock distribution network for microprocessors," IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 792-799, May 2001.
    [2] F. P. O’Mahony, "10Ghz Global Clock Distribution Using Coupled Standing-Wave Oscillators," Ph.D, Electrical Engineering, Stanford University, 2003.
    [3] I. S. Kourtev and E. G. Friedman, "A quadratic programming approach to clock skew scheduling for reduced sensitivity to process parameter variations," Proc. IEEE International ASIC/SOC Conf., pp. 210-215, Nov. 1999.
    [4] I. S. Kourtev and E. G. Friedman, "Simultaneous clock scheduling and buffered clock tree synthesis," in Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on, 1997, vol. 3, pp. 1812-1815 vol.3.
    [5] I. S. Kourtev and E. G. Friedman, "Clock skew scheduling for improved reliability via quadratic programming," Proc. IEEE/ACM International Conf. on Computer-Aied Design, pp. 239-243, 7-11 Nov. 1999.
    [6] B. Taskin and I. S. Kourtev, "Delay insertion method in clock skew scheduling," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 4, pp. 651-663, Apr. 2006.
    [7] W. Dally and J. Poulton, Digital Systems Engineering. Cambridge: Cambridge University Press, 1998.
    [8] Q. Zhu, High-speed clock network design. Boston: Kluwer Academic Publishers, 2003.
    [9] M. Horowitz, "Clocking strategies in high performance processors," in Symp. VLSI Circuits Digest of Technical Papers, 1992, pp. 50-53.
    [10] K. M. C. e. al, "A clock methodology for high-performance microprocessors," Journal of VLSI Signal Processing, vol. 16, pp. 217-24, 1997.
    [11] F. E. Anderson, J. S. Wells, and E. Z. Berta, "The core clock system on the next generation Itanium/spl trade/ microprocessor," in IEEE ISSCC Dig. Tech. Papers, 2002, vol. 1, pp. 146-453 vol.1.
    [12] D. W. Bailey and B. J. Benschneider, "Clocking design and analysis for a 600-MHz Alpha microprocessor," IEEE J. of Solid-State Circuits, vol. 33, no. 11, pp. 1627-1633, 1998.
    [13] P. Barnes, "A 500 MHz 64b RISC CPU with 1.5 MB on-chip cache," in IEEE ISSCC Dig. Tech. Papers, 1999, pp. 86-87.
    [14] N. Bindal, T. Kelly, N. Velastegui, and K. L. Wong, "Scalable sub-10ps skew global clock distribution for a 90nm multi-GHz IA microprocessor," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 346-498 vol.1.
    [15] G. Geannopoulos and X. Dai, "An adaptive digital deskewing circuit for clock distribution networks," in IEEE ISSCC Dig. Tech. Papers, 1998, pp. 400-401.
    [16] B. A. Gieseke et al., "A 600 MHz superscalar RISC microprocessor with out-of-order execution," in IEEE ISSCC Dig. Tech. Papers, 1997, pp. 176-177.
    [17] S. Hesley et al., "A 7/sup th/-generation x86 microprocessor," in IEEE ISSCC Dig. Tech. Papers, 1999, pp. 92-93.
    [18] P. Hofstee et al., "A 1 GHz single-issue 64 b PowerPC processor," in IEEE ISSCC Dig. Tech. Papers, 2000, pp. 92-93.
    [19] Y. Hoskote et al., "A 10GHz TCP offload accelerator for 10Gb/s Ethernet in 90nm dual-V/sub T/ CMOS," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 258-492 vol.1.
    [20] F. Ishihara, C. Klingner, and K. Agawa, "Clock design of 300 MHz 128-bit 2-way superscalar microprocessor," in in Proceedings of the ASP-DAC, 2000, pp. 647-652.
    [21] N. A. Kurd, J. S. Barkatullah, R. O. Dizon, T. D. Fletcher, and P. D. Madland, "Multi-GHz clocking scheme for Intel(R) Pentium(R) 4 microprocessor," in IEEE ISSCC Dig. Tech. Papers, 2001, pp. 404-405.
    [22] S. McMahan et al., "A 600 MHz NT3 network processor," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 256-257 vol.1.
    [23] C. Nicoletta et al., "A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect," IEEE J. Solid-State Circuits, vol. 34, no. 11, pp. 1478-1491, 1999.
    [24] G. Northrop et al., "609 MHz G5 S/399 microprocessor," in IEEE ISSCC Dig. Tech. Papers, 1999, pp. 88-89.
    [25] P. J. Restle et al., "The clock distribution of the Power4 microprocessor," in IEEE ISSCC Dig. Tech. Papers, 2002, vol. 1, pp. 144-145 vol.1.
    [26] P. J. Restle and A. Deutsch, "Designing the best clock distribution network," in Symp. VLSI Circuits Digest of Technical Papers, 1998, pp. 2-5.
    [27] P. J. Restle et al., "A clock distribution network for microprocessors," in Symp. VLSI Circuits Digest of Technical Papers, 2000, pp. 184-187.
    [28] S. Tam, S. Rusu, U. N. Desai, R. Kim, Z. Ji, and I. Young, "Clock generation and distribution for the first IA-64 microprocessor," IEEE J. of Solid-State Circuits, vol. 35, no. 11, pp. 1545-1552, 2000.
    [29] N. Vasseghi, K. Yeager, E. Sarto, and M. Seddighnezhad, "200-MHz superscalar RISC microprocessor," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1675-1686, 1996.
    [30] C. F. Webb et al., "A 400-MHz S/390 microprocessor," IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1665-1675, 1997.
    [31] T. Xanthopoulos, D. W. Bailey, A. K. Gangwar, M. K. Gowan, A. K. Jain, and B. K. Prewitt, "The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor," in IEEE ISSCC Dig. Tech. Papers, 2001, pp. 402-403.
    [32] S. Ganguly, D. Lehther, and S. Pullela, "Clock distribution methodology for PowerPC microprocessors," Journal of VLSI Signal Processing, vol. 16, pp. 181-9, 1997.
    [33] S. C. Chan, K. L. Shepard, and P. J. Restle, "Uniform-phase uniform-amplitude resonant-load global clock distributions," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 102-109, Jan. 2005.
    [34] F. O'Mahony, C. P. Yue, M. A. Horowitz, and S. S. Wong, "A 10-GHz global clock distribution using coupled standing-wave oscillators," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1813-1820, Nov. 2003.
    [35] M. Sasaki, M. Shiozaki, A. Mori, A. Iwata, and H. Ikeda, "12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique," IEEE ISSCC Dig. Tech. Papers, pp. 180-595, 2007.
    [36] M. Sasaki, "A 9.5GHz 6ps-Skew Space-Filling-Curve Clock Distribution with 1.8V Full-Swing Standing-Wave Oscillators," IEEE ISSCC Dig. Tech. Papers, pp. 518-633, 2008.
    [37] M. Sasaki, "A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators," IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2800-2807, Oct. 2009.
    [38] S. C. Chan, K. L. Shepard, and P. J. Restle, "Distributed Differential Oscillators for Global Clock Networks," IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2083-2094, Sep. 2006.
    [39] J. Wood, T. C. Edwards, and S. Lipa, "Rotary traveling-wave oscillator arrays: a new clock technology," IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1654-1665, Nov. 2001.
    [40] Y. Teng and B. Taskin, "ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. PP, no. 99, pp. 1-1, 2015.
    [41] K. Takinami, R. Walsworth, S. Osman, and S. Beccue, "Phase-Noise Analysis in Rotary Traveling-Wave Oscillators Using Simple Physical Model," IEEE Trans. Microw. Theory Techn., vol. 58, no. 6, pp. 1465-1474, Jun. 2010.
    [42] P. Restle and H. Xuejue, "Inductance: implications and solutions for high-speed digital circuits - clock distribution," IEEE ISSCC Dig. Tech. Papers, vol. 2, pp. 558-562, 7-7 Feb. 2002.
    [43] V. Sathe, S. Arekapudi, C. Ouyang, M. Papaefthymiou, A. Ishii, and S. Naffziger, "Resonant clock design for a power-efficient high-volume x86-64 microprocessor," in IEEE ISSCC Dig. Tech. Papers, 2012, pp. 68-70.
    [44] S. Chan et al., "A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 512-632.
    [45] V. M. e. al, "A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance," in in Proceedings of DAC, 2000, pp. 172-75.
    [46] Y. L. e. al., "Impact of interconnect variations on the clock skew of a gigahertz microprocessor," in in Proceedings of DAC, 2000, pp. 168-71.
    [47] Z. Qing and W. W. M. Dai, "High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models," IEEE Trans. Computer-Aided Design of Integrated Circuits, vol. 15, no. 9, pp. 1106-1118, 1996.
    [48] P. Zarkesh-Ha and J. D. Meindl, "Optimum chip clock distribution networks," in in Proceedings of the International Interconnect Technology Conference, 1999, pp. 18-20.
    [49] F. U. Rahman and V. S. Sathe, "Voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2V DVFS System," in IEEE ISSCC Dig. Tech. Papers, 2016, pp. 334-335.
    [50] A. T. Ishii, J. C. Kao, V. S. Sathe, and M. C. Papaefthymiou, "A resonant-clock 200MHz ARM926EJ-S microcontroller," in Proceedings of ESSCIRC, 2009, pp. 356-359.
    [51] P. Restle et al., "Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8 microprocessor," in IEEE ISSCC Dig. Tech. Papers, 2014, pp. 100-101.
    [52] A. J. Drake, K. J. Nowka, T. Y. Nguyen, J. L. Burns, and R. B. Brown, "Resonant clocking using distributed parasitic capacitance," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1520-1528, Sep. 2004.
    [53] L. Hall, M. Clements, L. Wentai, and G. Bilbro, "Clock distribution using cooperative ring oscillators," Proc. 17th Conf. Advanced Research in VLSI, pp. 62-75, 15-16 Sep 1997.
    [54] S. Deibele and J. B. Beyer, "Attenuation compensation in distributed amplifier design," IEEE Trans. Microw. Theory Techn., vol. 37, no. 9, pp. 1425-1433, Sep. 1989.
    [55] J. G. Maneatis and M. A. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1273-1282, Dec.1993.
    [56] T. Xanthopoulos, Clocking in modern VLSI systems. Dordrecht: Springer, 2009.
    [57] W. C. Athas, L. J. Svensson, J. G. Koller, N. Tzartzanis, and E. Y.-C. Chou, "Low-power digital systems based on adiabatic-switching principles," IEEE Trans. Very Large Scale Integration (VLSI) Systems vol. 2, no. 4, pp. 398-407, Dec. 1994.
    [58] D. B. Leeson, "A simple model of feedback oscillator noise spectrum," Proceedings of the IEEE, vol. 54, no. 2, pp. 329-330, 1966.
    [59] A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," Solid-State Circuits, IEEE Journal of, vol. 33, no. 2, pp. 179-194, 1998.
    [60] Y. A. Eken, "High Frequency Voltage Controlled Ring Oscillators in Standard CMOS," Ph.D, School of Electrical and Computer Engineering, Georgia Institute of Technology, 2003.
    [61] Science_X. (2016). Researchers prove Huygens was right about pendulum synchronization. Available: https://phys.org/news/2016-03-huygens-pendulum-synchronization.html
    [62] R. GRAY. (2015). Clocks 'SPEAK' to each other: The mystery of how pendulum clocks self-synchronise their ticks is solved after 350 years. Available: http://www.dailymail.co.uk/sciencetech/article-3176193/Clocks-SPEAK-Mystery-pendulum-clocks-synchronise-ticks-tocks-solved-350-years.html#ixzz4zEoxSoPd
    [63] R. Adler, "A Study of Locking Phenomena in Oscillators," Proc. IRE, vol. 34, no. 6, pp. 351-357, 1946.
    [64] B. V. D. Pol, "Forced oscillator in a circuit with nonlinear resistance," Phil. Mag., vol. 3, pp. 65-80, 1927.
    [65] B. v. d. Pol, "The Nonlinear Theory of Electric Oscillations," Proceedings of the Institute of Radio Engineers, vol. 22, no. 9, pp. 1051-1086, 1934.
    [66] C. Heng-Chia, C. Xudong, U. K. Mishra, and R. A. York, "Phase noise in coupled oscillators: theory and experiment," IEEE Trans. Microw. Theory Techn., vol. 45, no. 5, pp. 604-615, May 1997.
    [67] D. K. Shaeffer and S. Kudszus, "Performance-optimized microstrip coupled VCOs for 40-GHz and 43-GHz OC-768 optical transmission," IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1130-1138, Jul. 2003.
    [68] K. Kurokawa, "Noise in Synchronized Oscillators," IEEE Trans. Microw. Theory Techn., vol. 16, no. 4, pp. 234-240, Apr. 1968.
    [69] K. Kurokawa, "Injection locking of microwave solid-state oscillators," Proceedings of the IEEE, vol. 61, no. 10, pp. 1386-1410, Oct. 1973.
    [70] M. M. Abdul-Latif and E. Sanchez-Sinencio, "Low Phase Noise Wide Tuning Range N-Push Cyclic-Coupled Ring Oscillators," IEEE J. Solid-State Circuits, vol. 47, no. 6, pp. 1278-1294, Jun. 2012.
    [71] A. Mirzaei, M. E. Heidari, R. Bagheri, S. Chehrazi, and A. A. Abidi, "The Quadrature LC Oscillator: A Complete Portrait Based on Injection Locking," IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1916-1932, Sep. 2007.
    [72] A. Mirzaei, M. E. Heidari, R. Bagheri, and A. A. Abidi, "Multi-Phase Injection Widens Lock Range of Ring-Oscillator-Based Frequency Dividers," IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 656-671, Mar. 2008.
    [73] B. Razavi, "A study of injection locking and pulling in oscillators," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, Sept. 2004.
    [74] A. V. Oppenheim, Signals & systems. Upper Saddle River: Prentice Hall, 1997.
    [75] J. J. Kuffner and S. M. LaValle, "Space-filling trees: A new perspective on incremental search for motion planning," IEEE/RSJ Int. Conf. on Intel. Rob. and Sys. (IROS), pp. 2199-2206, 25-30 Sept. 2011.
    [76] S. Verma, J. Xu, and T. H. Lee, "A Multiply-by-3 Coupled-Ring Oscillator for Low-Power Frequency Synthesis," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 709-713, Apr. 2004.
    [77] F. Herzel and B. Razavi, "A study of oscillator jitter due to supply and substrate noise," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, vol. 46, no. 1, pp. 56-62, Jan. 1999.
    [78] Y. Xiaohua, A. El-Gouhary, and N. M. Neihart, "A Transformer-Based Dual-Coupled Triple-Mode CMOS LC-VCO," Microwave Theory and Techniques, IEEE Transactions on, vol. 62, no. 9, pp. 2059-2070, 2014.
    [79] S. Yi, K. F. Tsang, L. Wah Ching, H. Faan Hei, I. F. Triantis, and X. Kai, "Design of low-phase-noise CMOS transformer-based gate-coupled quadrature VCO," Electronics Letters, vol. 50, no. 6, pp. 434-436, 2014.
    [80] S. Jain and J. Sheng-Lyang, "Triple-Band Transformer-Coupled LC Oscillator With Large Output Voltage Swing," Microwave and Wireless Components Letters, IEEE, vol. 24, no. 7, pp. 475-477, 2014.
    [81] A. El-Gouhary and N. M. Neihart, "An Analysis of Phase Noise in Transformer-Based Dual-Tank Oscillators," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 61, no. 7, pp. 2098-2109, 2014.
    [82] M. Garampazzi, P. M. Mendes, N. Codega, D. Manstretta, and R. Castello, "Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator With Transformer-Based Tail Filtering," Solid-State Circuits, IEEE Journal of, vol. 50, no. 7, pp. 1657-1668, 2015.
    [83] A. Mazzanti and A. Bevilacqua, "On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 62, no. 9, pp. 2334-2341, 2015.
    [84] D. Manstretta and R. Castello, "An intuitive analysis of phase noise fundamental limits in LC oscillators," in Noise and Fluctuations (ICNF), 2015 International Conference on, 2015, pp. 1-6.
    [85] C. H. Huang, Y. C. Lin, T. S. Horng, and L. T. Hwang, "Design of compact bandpass filter using transformer-based coupled resonators on integrated passive device glass substrate," presented at the Asia-Pacific Microwave Conference, Melbourne, 2011.
    [86] T. M. Hollis and D. J. Comer, "Bandpass Filtering of High-Speed Forwarded Clocks," J. of Analog Integr Circ Sig Process, vol. 54, no. no. 3, pp. pp. 171-184, Mar. 2008.
    [87] H. Song, J. Song, A. Dey, and Y. Song, "Jitter transfer function model and VLSI jitter filter circuits," IEEE SOCC, 2010.
    [88] K. S. S. Kumar, Electric circuits and networks. New Delhi, India: Dorling Kindersely, p. 667-673 2009, pp. 667-673.
    [89] R. A. Robinson. Cascaded Filters Transfer Function. Available: https://zh-tw.coursera.org/learn/electronics/lecture/0WXgO/3-8-extra-cascaded-filters-transfer-function
    [90] B. J. Maundy and A. S. Elwakil, "Second order bandstop and bandpass filters using transformers," Microelectronics Journal, vol. 46, no. 8, pp. 690-697, 2015/08/01/ 2015.
    [91] A. Zolfaghari, A. Chan, and B. Razavi, "Stacked inductors and transformers in CMOS technology," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-628, Apr. 2001.
    [92] B. Ganesh and S. Naresh, "Modeling and mitigation of jitter in high-speed source-synchronous interchip communication systems," The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, vol. 2, pp. 1681-1687, 2003.
    [93] A. Ragab, Y. Liu, K. Hu, P. Chiang, and S. Palermo, "Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links," Journal of Electrical and Computer Engineering, vol. 2011, p. 15, 2011, Art. no. 982314.
    [94] Y. Liu, "Jitter Tracking Bandwidth Optimization Using Active-Inductor-Based Bandpass Filtering in High-Speed Forwarded Clock Transceivers," MS, Electrical Engineering, Texas A&M University, 2011.
    [95] H. In-Chul, K. Chulwoo, and K. Sung-Mo, "A CMOS self-regulating VCO with low supply sensitivity," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 42-48, Jan. 2004.
    [96] A. Hajimiri and T. H. Lee, "Design issues in CMOS differential LC oscillators," Solid-State Circuits, IEEE Journal of, vol. 34, no. 5, pp. 717-724, May 1999.
    [97] S. Choi, S. Yoo, Y. Lim, and J. Choi, "A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector," IEEE J. Solid-State Circuits, vol. 51, no. 8, pp. 1878-1889, Aug. 2016.
    [98] I. Galton, D. A. Towne, J. J. Rosenberg, and H. T. Jensen, "Clock distribution using coupled oscillators," in in Proc. IEEE Int. Symp. Circuits and Systems, 1996, vol. 3, pp. 217-220 vol.3.
    [99] H. Mizuno and K. Ishibashi, "A noise-immune GHz-clock distribution scheme using synchronous distributed oscillators," in IEEE ISSCC Dig. Tech. Papers, 1998, pp. 404-405.
    [100] Z. Bai, X. Zhou, R. D. Mason, and G. Allan, "Low-Phase Noise Clock Distribution Network Using Rotary Traveling-Wave Oscillators and Built-In Self-Test Phase Tuning Technique," IEEE Trans. Circuits Syst. II, Express Briefs, vol. 62, no. 1, pp. 41-45, Jan. 2015.
    [101] S. K. Lim, "Low Power Clock Routing for 3D IC," in Design for High Performance, Low Power, and Reliable 3D Integrated CircuitsNew York, NY: Springer New York, 2013, pp. 99-128.
    [102] V. F. Pavlidis, I. Savidis, and E. G. Friedman, "Clock distribution networks for 3-D ictegrated Circuits," in 2008 IEEE Custom Integrated Circuits Conference, 2008, pp. 651-654.
    [103] V. F. Pavlidis, I. Savidis, and E. G. Friedman, "Clock Distribution Networks in 3-D Integrated Systems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 12, pp. 2256-2266, 2011.
    [104] Y. Take, N. Miura, H. Ishikuro, and T. Kuroda, "3D clock distribution using vertically/horizontally-coupled resonators," in IEEE ISSCC Dig. Tech. Papers, 2013, pp. 258-259.
    [105] Y. Take, J. Kadomoto, and T. Kuroda, "3D integration using inductive coupling and coupled resonator (Invited)," in 2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2015, pp. 46-48.
    [106] U. R. Tida, V. Mittapalli, C. Zhuo, and Y. Shi, "Opportunistic through-silicon-via inductor utilization in LC resonant clocks: Concept and algorithms," in 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2014, pp. 750-757.
    [107] S. J. Wang, C. H. Lin, and K. S. M. Li, "Synthesis of 3D clock tree with pre-bond testability," in 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013, pp. 2654-2657.
    [108] L. Woojin, K. Jaemin, R. Chunghyun, P. Jongbae, K. Jun Chul, and K. Joungho, "A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator," Microwave and Wireless Components Letters, IEEE, vol. 19, no. 8, pp. 512-514, 2009.
    [109] H. Nijmeijer. Synchronization of Huygens‘ clocks: old and new. Available: https://static.tue.nl/fileadmin/content/onderzoek/Institute_for_Complex_Molecular_Systems_-_ICMS/Agenda/NijmeijerICMS2017.pdf
    [110] H. Xuchu and M. R. Guthaus, "Distributed LC Resonant Clock Grid Synthesis," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 59, no. 11, pp. 2749-2760, 2012.
    [111] V. L. Chi, "Salphasic distribution of clock signals for synchronous systems," IEEE Trans. Comput., vol. 43, no. 5, pp. 597-602, May 1994.

    QR CODE