近年來，嵌入式記憶體已經是系統晶片（System-on-Chip）中一種廣泛使用的重要元件。隨著製程技術的發展，記憶體核心越來越稠密，佔據整個系統晶片中大部份的面積，並且決定了整個晶片的良率。因此，對一個系統晶片產品來說，將記憶體的良率保持在一個合理的水準是很重要的。基於這個目的，記憶體設計者通常使用備用的記憶體元件來修復主記憶體上的缺陷，以改善出貨良率。然而，即便是在相同的製程技術之下，不同的主記憶體設計以及備援記憶體架構亦可能導致截然不同的修復效率以及良率。為了在合理代價之下得到最高良率，記憶體的備援分析(Redundancy Analysis)是不可或缺的。

為了更容易地評估記憶體修復效率，我們提出了一個備援分析模擬器。透過一個系統化的記憶體結構以及備援記憶體使用限制表示方法，模擬器可以針對各式各樣不同的記憶體設計進行模擬，配合使用者指定的備援分析演算法，得到相對應的修復率以及良率，以供記憶體設計者用作評估或是修改設計時的參考。此外，我們亦提出了數個可以提前終止分析運算的簡單判斷法則，並實現於模擬器之中，以縮短費時的備援分析模擬運算時間。實驗數據驗證了我們的備援分析模擬器確實能有效率地對在備援記憶體使用限制之下的記憶體架構以及備援分析演算法進行評估。

Embeddedmemory is one of themost widely used cores in current system-on-chip (SOC). Memory
cores are more and more compact, and dominate the silicon area and yield of the chip. However,
caused by process variation and some defects, how to maintain the yield of memory is an important
issue. Today, redundancy repair methodology is widely used to enhance memory yield. Different
memory and redundancy architecture may lead to different efficiency of redundancy repair and
thus final yield under a specific process.

In this work, we propose a redundancy analysis (RA) algorithm simulation tool to evaluate the
efficiency of repair. The RA simulator reports the repair rate (the ratio of the reparable memory
count to the defective memory count) and yield (after repair) with given RA algorithm, associated
memory configuration, and redundancy structure. We have defined a systematic representation
method to describe memory architecture and redundancy constraint. With our tool, the user can
easily evaluate and plan the memory architecture and redundant elements. To reduce the simulation
time, some early terminate criteria are developed and implemented. Experimental results show that
our RA simulator can effectively evaluate the RA algorithm and memory structure, considering
redundancy constraints.

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