在本論文第一部份，提出利用氧化矽-氮化矽-氧化矽(ＯＮＯ)堆疊閘極介電層及多重奈米線（nanowire）結構來改善多晶矽薄膜電晶體(ＴＦＴ)的特性。實驗結果指出，由於氧化矽-氮化矽-氧化矽堆疊閘極介電層相較於傳統氧化矽閘極介電層具有較高之介電常數，元件特性因此受到改善。除此之外，具有多重奈米線結構之薄膜電晶體有較佳之電性特性。由於閘極之電力線會聚集在奈米線狹窄的通道表面，且形成大的電場，所以具奈米線結構之元件會有較佳之閘極控制能力。因此，具奈米線結構之SONOS-TFT的元件特性主要的改善來自於電力線聚集所產生的高電場效應。此外，SONOS-TFT在適當的電壓操作下亦可具有非揮發性記憶體之功能。在此，所提出之奈米線SONOS-TFT因具有較好之閘極控制能力，所以有較快的寫入/抹除效率。
接下來，當氧化矽-氮化矽-氧化矽堆疊閘極介電層的膜厚比多晶矽薄膜之後度還要薄時，奈米線結構SONOS-TFT的奈米線通道會被多晶矽閘極給包覆。由實驗結果顯示，由於三向閘極及額外的轉角電流貢獻，使奈米線結構SONOS-TFT具有較佳之電性特性。由電場模擬結果驗證，奈米線結構SONOS-TFT的寫入/抹除效率之改善，主要是由於較多的轉角數目及其轉角效應所貢獻。相同地，電場的模擬結果也顯示出，在轉角區域裡，跨越穿隧氧化層之電場被增強，而跨越阻擋氧化層之電場卻是降低的。在記憶體操作時，這樣的電場分佈可以抑制寄生的閘極注入效應，使得抹除速度能明顯地改善。此外，這樣的元件也具有良好之耐操度與資料保存特性。
最後，我們利用Π型閘極結構於奈米線通道，製作出整合非揮發性矽-氧-氮-氧-矽(SONOS)之多晶矽薄膜電晶體（TFT）。此Π型閘極SONOS-TFT具有較佳之電晶體電性，如較小之啟始電壓與較陡峭之次臨界斜率。由輸出特性顯示，此元件亦具有較高之驅動電流，且可抑制扭結效應(Kink-effect)。在記憶體的應用上，在適當的電壓操作下，此元件能提供較快之寫入/抹除效率及較大之啟始電壓飄移。此Π型閘極SONOS-TFT的電性改善都是由其較大的有效通道寬度及較多之轉角數目所貢獻。

In first part, presents a method to enhance the performance of polycrystalline silicon thin film transistors (ploy-Si TFTs) by using an oxide-nitride-oxide (ONO) gate dielectric and the multiple nanowire channels structure. Experimental results indicate that the performance of the device was enhanced by using the ONO multilayer, because the ONO gate dielectric constant is increased compared to the conventional oxide gate dielectric. Additionally, the TFTs with a ten nanowire channel structure (NW-TFTs) have superior electrical characteristics than other TFTs. Since the crowding of the gate fringing field at the narrow channel surface of nanowire causes the large electrical field, the devices with nanowire structure have the better gate control ability. Hence, the device characteristics of SONOS-TFT with NW structure are mainly improved by the high electrical field originated from fringing electrical field effect. Furthermore, the SONOS-TFT also can be functioned as a nonvolatile memory under adequate bias operation. The proposed NW SONOS-TFT can exhibit high program/erase (P/E) efficiency due to the good gate control ability originated from fringing electrical field effects.
Next, as the thickness of ONO layer thinner than that of poly-Si channel, the SONOS-TFT with nanowire channels is surrounded by poly-gate. The experimental results show that the NW SONOS-TFT has the superior electrical characteristics due to the tri-gate structure and additional corner current induced by corner effect. The simulation of electrical field results verified that the enhancement of P/E efficiency in NW SONOS-TFT is mainly attributed to the large number of corners and their corner effect. Also, the simulation result on electrical field reveals that the electrical field across the tunnel oxide is enhanced and that across the blocking oxide is reduced at the corner regions. This will lead the parasitic gate injection activity and the erasing speed can be apparently improved in the memory device, due to the pronounced corner effect and narrow channel width. In addition, the good endurance and retention are also obtained in this device.
Finally, we apply the pi-gate structure on nanowire channel for polycrystalline silicon thin-film transistor (poly-SiTFT) combined with nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory. The proposed pi-gate TFT-SONOS has superior electrical characteristics of transistor, such as smaller threshold voltage (Vth) and steeper subthreshold slope (SS). The output characteristic also exhibits the high driving current and suppression of the kink-effect. For memory application, the device can provide high program/erase (P/E) efficiency and large threshold voltage shift under adequate bias operation. The enhanced performance for pi-gate SONOS-TFT is attributed to the larger effective channel width and number of corners.

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Chapter 5
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Chapter 6
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Chapter 7
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