簡易檢索 / 詳目顯示

回結果列表
研究生： 李孟憬
Li, Meng-Jing
論文名稱： 以建構性的方法來進行臨界函數辨識的研究
A Constructive Approach for Threshold Function Identification
指導教授： 王俊堯
Wang, Chun-Yao
口試委員: 江介宏
Jiang, Jie-Hong
温宏斌
Wen, Hung-Pin
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年： 2022
畢業學年度： 110
語文別： 英文
論文頁數： 27
中文關鍵詞： 臨界邏輯 、臨界值邏輯閘 、臨界函數辨識
外文關鍵詞： Threshold logic, Linear threshold logic gate, Threshold function identification
相關次數： 點閱：2  下載：0 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 臨界函數是布林函數的子集，可以被單一臨界邏輯閘呈現的布林函數是臨界函數。在臨界邏輯的研究中，臨界函數的識別方法是一個很基本的工作，它決定一個布林函數是否為臨界函數。在此研究中，我們提出了文獻上第一個很實用的臨界函數之充分必要條件。藉由我們所提出的充分必要條件，我們設計了一個更有效率的臨界函數識別的演算法。根據實驗結果，與最先進的臨界函數識別方法相比，我們所提出的方法在識別所有8輸入臨界函數時節省了93%的時間。此外，通過提出的方法識別的臨界函數所對應臨界邏輯閘，有更多臨界邏輯閘擁有最小的權重和臨界值。

    Threshold Function (TF) is a subset of Boolean function that can be represented with a single linear threshold gate (LTG). In the research about threshold logic, the identification of TF is an important task that determines whether a given function is a TF or not. In this paper, we propose the first practical sufficient and necessary condition for a function being a TF in the literature. With the proposed sufficient and necessary condition, we devise a TF identification algorithm. The experimental results show that the proposed approach saves 93% CPU time for identifying all the 8-input NP-class TFs as compared with the state-of-the-art. Furthermore, the LTGs corresponding to the identified TFs obtained by the proposed approach have the minimum weights and threshold value for more TFs than the state-of-the-art.

    中文摘要 i Abstract ii Acknowledgement iii Contents iv List of Tables vi List of Figures vii 1 Introduction 1 2 Preliminaries 5 2.1 Hyperplane and Half-Space 5 2.2 Chow’s Parameter 5 2.3 Shannon’s Expansion 6 2.4 Equivalence Classes 6 3 Threshold Function Identification 8 3.1 Review of the State-of-the-Art 8 3.2 Sufficient and Necessary Condition for Function Being TF 11 3.3 Composite Inequality System Generation 13 3.4 Weight Assignment and Threshold Value Computation 16 3.5 New Initial Weight Assignment 17 3.6 Overall Flow 19 4 Experimental Results 21 5 Conclusion and Future Work 24

    [1] M. J. Avedillo, J. M. Quintana, H. Pettenghi, P. M. Kelly, and C. J. Thompson, “Multi-threshold Threshold Logic Circuit Design Using Resonant Tunnelling Devices,” Electron. Lett., vol. 39, no. 21, pp. 1502–1504, Oct. 2003.
    [2] Y.-C. Chen, H.-J. Chang, and L.-C. Zheng, “Don’t-Care-Based Node Minimization for Threshold Logic Networks,” in Proc. DAC, 2020.
    [3] D. Goldharber-Gordon, M. S. Montemerlo, J. C. Love, G. J. Opiteck, and J. C. Ellenbogen, “Overview of Nanoelectronic Devices,” in Proc. IEEE, vol. 85, no. 4, pp. 521–540, Apr. 1997.
    [4] W.-C. Hsu, C.-C. Lin, Y.-T. Li, Y.-C. Chen and C.-Y. Wang, “On Reduction of Computations for Threshold Function Identification,” in Proc. SOCC, 2021, pp. 146-151.
    [5] P.-Y. Kuo, C.-Y. Wang and C.-Y. Huang, “On Rewiring and Simplification for Canonicity in Threshold Logic Circuits,” in Proc. ICCAD, 2011, pp. 396-403.
    [6] Y.-A. Lai, C.-C. Lin, C.-C. Wu, Y.-C. Chen, and C.-Y. Wang, “Efficient Synthesis of Approximate Threshold Logic Circuits with an Error Rate Guarantee,” in Proc. DATE, 2018, pp. 773–778.
    [7] S.-Y. Lee, N.-Z. Lee, and J.-H. R. Jiang, “Canonicalization of Threshold Logic Representation and Its Applications,” in Proc. ICCAD, 2018, pp. 1-8.
    [8] C.-H. Liu, C.-C. Lin, Y.-C. Chen, C.-C. Wu, C.-Y. Wang, and S. Yamashita, “Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 38, no. 12, pp. 2284–2297, Dec. 2019.
    [9] C.-C. Lin, C.-W. Huang, C.-Y.Wang, and Y.-C. Chen, “In&Out: Restructuring for threshold logic network optimization,” in Proc. ISQED, 2017, pp. 413-418.
    [10] C.-C. Lin, C.-H. Liu, Y.-C. Chen, and C.-Y. Wang, “A New Necessary Condition for Threshold Function Identification,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 39, no. 12, pp. 5304-5308, Dec. 2020.
    [11] C.-C. Lin, C.-S. Lin, Y.-H. Tsai, Y.-C. Chen, and C.-Y. Wang, “Don’t Care Computation and De Morgan Transformation for Threshold Logic Network Optimization,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 41, no. 5, pp. 1412-1422, May 2022.
    [12] C.-C. Lin, C.-Y. Wang, Y.-C. Chen, and C.-Y. Huang, “Rewiring for Threshold Logic Circuit Minimization,” in Proc. DATE, 2014, pp. 1–6.
    [13] S. Muroga, I. Toda, and M. Kondo. “Majority Decision Functions of up to Six Variables.” Mathematics of Computation, vol. 16, no. 80, pp. 459-472, 1962.
    [14] S. Muroga, T. Tsuboi, and C. R. Baugh, “Enumeration of Threshold Functions of Eight Variables,” IEEE Trans. on Computers, vol. C-19, no. 9, pp. 818-825, Sep. 1970.
    [15] S. Muroga, Threshold Logic and its Applications. New York, NY, USA: Wiley, 1971.
    [16] A. Neutzling, M. G. A. Martins, V. Callegaro, A. I. Reis, and R. P. Ribas, “A Simple and Effective Heuristic Method for Threshold Logic Identification,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 37, no. 5, pp. 1023–1036, May 2018.
    [17] V. A. Mardiris, G. C. Sirakoulis, and I. G. Karafyllidis, “Automated Design Architecture for 1-D Cellular Automata Using Quantum Cellular Automata,” IEEE Trans. Comput., vol. 64, no. 9, pp. 2476–2489, Sep. 2015.
    [18] G. Papandroulidakis, A. Serb, A. khiat, G. Merreet, and T. Prodromakis, “Practical Implementation of Memristor-Based Threshold Logic Gates,” IEEE Trans. on Circuits and Systems, vol. 66, no. 8, pp. 3041-3051, 2019.
    [19] V. Saripalli, L. Liu, S. Datta, and V. Narayanan, “Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits,” J. Low Power Electron., vol. 6, no. 3, pp. 415–428, 2010.
    [20] C.-K. Tsai, C.-Y. Wang, C.-Y. Huang and Y.-C. Chen, “Sensitization Criterion for Threshold Logic Circuits and its Application,” in Proc. ICCAD, 2013, pp. 226-233.
    [21] R. O. Winder, “Single stage threshold logic,” in Proc. Switch. Circuit Theory Logical Design, 1961, pp. 321–332.
    [22] R. O. Winder, “Enumeration of Seven-Argument Threshold Functions,” in IEEE Transactions on Electronic Computers, vol. EC-14, no. 3, pp. 315-325, June 1965.
    [23] R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, “Threshold Network Synthesis and Optimization and Its Application to Nanotechnologies,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 1, pp. 107–118, Jan. 2005.

    QR CODE