鑑於 AR/VR 與自動駕駛汽車技術的快速發展，LiDAR 系統的作用日益重要，這些系統利用飛行時間 (TOF) 計算來確定距離，依賴於雷射發射及其反射回波的時間。隨著 LiDAR 裝置的廣泛採用，抗干擾、抗阻斷能力和裝置微型化等因素變得至關重要。光學混沌 LiDAR 系統藉由產生隨機混沌信號，以其強大的抗干擾和抗干擾特性而聞名，然而光學元件複雜且體積龐大，因此阻礙了其微型化的可能。因此以數位sample-based的混沌 LiDAR 系統利用數位電路產生以sample-based的隨機訊號，避開了對繁瑣光學元件的需求，這種方法保留了抗干擾和抗阻斷的優點，並大大有助於系統的微型化和便攜性。儘管如此，此技術仍面臨幾個迫切的問題：(1) 混沌隨機數字產生器 (CRNG) 的隨機性不足；(2) 系統的穩健性受到影響，許多初始值無法使用；(3) 數位電路的硬體使用率和效率缺乏優化。為了克服這些挑戰，本論文提出了 CRNG 與混沌雜訊產生器 (CNG) 的強化方案，目的在於改善數位電路處理器的效能與可靠性。
透過一系列的修改，提出的 CRNG 得到了顯著的提升，整合尤拉方法來求解修正的勞倫茲系統，在穩健性和硬體最佳化方面都有顯著的改善。在後處理單元中採用了所提出修正模一運算，產生符合所需隨機性標準的隨機數序列。此外，預處理單元利用週期性的擾動來確保這些序列的非週期性和不可預測性。CNG 處理器經過精心的硬體改良，專為平行 Box-Muller 處理器量身打造，達到最佳硬體效率。
研究成果驗證了所提出的 CRNG 能達到足夠的隨機性，通過 NIST-800-22 統計測試和增強穩健性。提出的 CRNG 和 CNG 處理器是在 Xilinx Virtex-7 VC707 FPGA 平台上實作，CRNG 處理器在 256.41 MHz 的時脈速度下達到 24.6153 Gbps 的顯著吞吐量，而 CNG 處理器在 200 MHz 的時脈速度下達到 1.2 Gsamples/s，與現有的隨機數字產生器 (RNG) 和雜訊產生器 (NG) 相比，所提出的 CRNG 和 CNG 處理器具有最高的吞吐量和硬體效率。此外，該研究實作台積電 40nm CMOS 技術的 tape-out 晶片，其中 CRNG 處理器在 232.8 MHz 時的吞吐量達到 22.348 Gbits/s，而 CNG 處理器在 268 MHz 時的吞吐量達到 1.608 Gsamples/s，與現有以 ASIC 為基礎的真亂數產生器 (TRNG) 相比，CRNG 處理器的吞吐量最高。在應用於數位sample-based的混沌 LiDAR 系統中，所提出的 CNG 可提供高幀率，滿足自動駕駛應用的要求。

In light of the rapid advancements in AR/VR and autonomous vehicle technologies, the role of LiDAR systems is increasingly critical. These systems utilize time of flight (TOF) calculations to determine distances, relying on the emission of a laser and the timing of its reflected return. Amidst the widespread adoption of LiDAR devices, factors such as antiinterference, anti-jamming capabilities, and device miniaturization are paramount. Optical chaos LiDAR systems are renowned for their robust anti-interference and anti-jamming properties due to the generation of random chaos signals. However, their miniaturization efforts are hindered by their reliance on complex and voluminous optical components. Therefore, the digital sample-based chaos LiDAR system utilizes digital circuits to generate sample-based random signals, circumventing the need for cumbersome optical components. This approach retains the anti-interference and anti-jamming benefits and significantly contributes to the system’s miniaturization and portability. Nevertheless, the technology faces several pressing issues: (1)The chaos random number generator (CRNG) exhibits inadequate randomness; (2)The system’s robustness is compromised, with many initial values proving non-viable; (3)The digital circuit has suboptimal hardware utilization and efficiency. To overcome these challenges, this thesis proposes enhancements to the CRNG and the chaos noise generator (CNG), aiming to improve the performance and reliability of the digital circuit processors.
The proposed CRNG is significantly enhanced through a series of modifications. The integration of the Euler method for solving the modified Lorenz system lead to notable improvements in robustness and hardware optimization. The proposed modified modulo-one operation is employed in the post-processing unit, generating random number sequences that meet the desired randomness criteria. Additionally, the pre-processing unit utilizes periodic perturbation to ensure the aperiodicity and unpredictability of these sequences. Moreover, the CNG processor undergoes meticulous hardware refinement, specifically tailored for parallel Box-Muller processors, achieving optimal hardware efficiency.
The research results validate the proposed CRNG as achieving sufficient randomness, as evidenced by passing the NIST-800-22 statistical test and enhancing robustness. The proposed CRNG and CNG processors were implemented in the Xilinx Virtex-7 VC707 FPGA platform. The CRNG processor achieves a remarkable throughput of 24.6153 Gbps at a clock speed of 256.41 MHz, while the CNG processor achieves 1.2 Gsamples/s at 200 MHz. In comparison with existing random number generators (RNGs) and noise generators (NGs), the proposed CRNG and CNG processors have the highest throughput and hardware efficiency. Furthermore, the research involved a tape-out chip utilizing TSMC’s 40nm CMOS technology, with the CRNG processor achieving a throughput of 22.348 Gbits/s at 232.8 MHz and the CNG processor achieving a throughput of 1.608 Gsamples/s at 268 MHz. Compared with existing ASIC-based true random number generators (TRNGs), the CRNG processor achieves the highest throughput. In the digital sample-based chaos LiDAR system, the proposed CNG can provide a high frame rate for the requirements of autonomous vehicle applications.

[1] C.-H. Cheng, C.-Y. Chen, J.-D. Chen, D.-K. Pan, K.-T. Ting, and F.-Y. Lin, “3D pulsed chaos lidar system,” Optics express, vol. 26, no. 9, pp. 12 230–12 241, 2018.
[2] L. Feng, H. Gao, J. Zhang, M. Yu, X. Chen, W. Hu, and L. Yi, “FPGA-based digital chaotic anti-interference lidar system,” Optics Express, vol. 29, no. 2, pp. 719–728, 2021.
[3] T. Chen, “Fpga-based chaos random number generator for chaos lidar system,” Master’s thesis, National Tsing Hua University, Taiwan, 2023.
[4] C.-C. Chang, “Study of random light source for random-modulation LiDAR based on direct current modulation,” Master’s thesis, National Tsing Hua University, Taiwan, 2022.
[5] C.-B. Chen, T. Chen, Y.-H. Huang, and Y.-H. Huang, “35.56-Gbits/sec Chaos Random Number Generator Supporting 1.2-GSamples/sec Noise Generation,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2023.
[6] L. Wang, Y. Xu, Y. Li, and Y. Zhao, “Voxel segmentation-based 3D building detection algorithm for airborne LIDAR data,” Plos one, vol. 13, no. 12, p. e0208996, 2018.
[7] Y. Li and J. Ibanez-Guzman, “Lidar for Autonomous Driving: The principles, challenges, and trends for automotive lidar and perception systems,” IEEE Signal Processing Magazine, vol. 37, no. 4, pp. 50–61, 2020.
[8] E.-L. Hsiang, Z. Yang, Q. Yang, P.-C. Lai, C.-L. Lin, and S.-T. Wu, “AR/VR light engines: perspectives and challenges,” Advances in Optics and Photonics, vol. 14, no. 4, pp. 783–861, 2022.
[9] V. Milanovi´c, A. Kasturi, J. Yang, and F. Hu, “A Fast Single-Pixel Laser Imager for VR/AR Headset Tracking,” in MOEMS and Miniaturized Systems XVI, vol. 10116. SPIE, 2017, pp. 91–99.
[10] M.-C. Amann, T. M. Bosch, M. Lescure, R. A. Myllylae, and M. Rioux, “Laser ranging: a critical review of usual techniques for distance measurement,” Optical engineering, vol. 40, pp. 10–19, 2001.
[11] G. Kim, J. Eom, and Y. Park, “Investigation on the occurrence of mutual interference between pulsed terrestrial LIDAR scanners,” in 2015 IEEE Intelligent Vehicles Symposium (IV). IEEE, 2015, pp. 437–442.
[12] X. Ai, R. Nock, J. G. Rarity, and N. Dahnoun, “High-resolution random-modulation cw lidar,” Applied optics, vol. 50, no. 22, pp. 4478–4488, 2011.
[13] W. Xiong, Q. Bai, Y. Hu, X. Zhang, Y. Wu, G. Xia, H. Zhou, J. Wu, and Z. Wu, “3D parallel pulsed chaos LiDAR system,” Optics Express, vol. 32, no. 7, pp. 11 763–11 773, 2024.
[14] F.-Y. Lin and J.-M. Liu, “Chaotic Lidar,” IEEE journal of selected topics in quantum electronics, vol. 10, no. 5, pp. 991–997, 2004.
[15] W. L. Lin, “Real-time FPGA System for Chaos LiDAR Depth Map and its Alignment Method with Camera Images,” Master’s thesis, National Tsing Hua University, Taiwan, 2019.
[16] S. Tatsunori, “A 10 Frames/Sec Real-Time Depth Map FPGA System for Chaos LiDAR Systems,” Master’s thesis, National Tsing Hua University, Taiwan, 2020.
[17] M. Ashtiyani, P. M. Birgani, and H. M. Hosseini, “Chaos-Based Medical Image Encryption Using Symmetric Cryptography,” in 2008 3rd International Conference on Information and Communication Technologies: From Theory to Applications. IEEE, 2008, pp. 1–5.
[18] N. Deepa and N. Sivamangai, “A State-Of-Art Model of Encrypting Medical Image Using DNA Cryptography and Hybrid Chaos Map - 2d Zaslavaski Map: Review,” in 2022 6th International Conference on Devices, Circuits and Systems (ICDCS). IEEE, 2022, pp. 190–195.
[19] I. Koyuncu and A. T. O¨ zcerit, “The design and realization of a new high speed FPGA-based chaotic true random number generator,” Computers & Electrical Engineering, vol. 58, pp. 203–214, 2017.
[20] M. Azzaz, C. Tanougast, S. Sadoudi, and A. Dandache, “Real-time FPGA Implementation of Lorenz’s Chaotic Generator for Ciphering Telecommunications,” in 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference. IEEE, 2009, pp. 1–4.
[21] M. Garcia-Bosque, A. P´erez-Resa, C. S´anchez-Azqueta, C. Aldea, and S. Celma, “Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA,” IEEE Transactions on Instrumentation and Measurement, vol. 68, no. 1, pp. 291–293, 2018.
[22] F. Yu, L. Li, B. He, L. Liu, S. Qian, Y. Huang, S. Cai, Y. Song, Q. Tang, Q. Wan et al., “Design and FPGA Implementation of a Pseudorandom Number Generator Based on a Four-Wing Memristive Hyperchaotic System and Bernoulli Map,” IEEE Access, vol. 7, pp. 181 884–181 898, 2019.
[23] K. Puntsri, B. Bunsri, Y. Pittayang, T. Bubpawan, W. Partipralam, and W. Phakphisut, “Reconfigurable AWGN Generator Using BoxMuller Method with CORDIC-Based Square Root Calculation,” in 2022 37th International Technical Conference on Circuits/ Systems, Computers and Communications (ITC-CSCC). IEEE, 2022, pp. 1–4.
[24] D.-U. Lee, W. Luk, J. D. Villasenor, and P. Y. Cheung, “A Gaussian Noise Generator for Hardware-Based Simulations,” IEEE Transactions on Computers, vol. 53, no. 12, pp. 1523–1534, 2004.
[25] D.-U. Lee, W. Luk, J. D. Villasenor, G. Zhang, and P. H. W. Leong, “A Hardware Gaussian Noise Generator Using the Wallace Method,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 8, pp. 911–920, 2005.
[26] G. Zhang, P. H. W. Leong, D.-U. Lee, J. D. Villasenor, R. C. Cheung, and W. Luk, “Ziggurat-based hardware Gaussian random number generator,” in International Conference on Field Programmable Logic and Applications, 2005. IEEE, 2005, pp. 275– 280.
[27] J. Su and J. Han, “An improved Ziggurat-based hardware Gaussian random number generator,” in 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2016, pp. 1606–1608.
[28] A. Rukhin, J. Soto, J. Nechvatal, M. Smid, E. Barker, S. Leigh, M. Levenson, M. Vangel, D. Banks, A. Heckert et al., A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications. US Department of Commerce, Technology Administration, National Institute of . . . , 2001, vol. 22.
[29] A. S. Elwakil and M. P. Kennedy, “Construction of Classes of Circuit-Independent Chaotic Oscillators Using Passive-Only Nonlinear Devices,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 48, no. 3, pp. 289–307, 2001.
[30] L. M. Pecora, T. L. Carroll, G. A. Johnson, D. J. Mar, and J. F. Heagy, “Fundamentals of synchronization in chaotic systems, concepts, and applications,” Chaos: An Interdisciplinary Journal of Nonlinear Science, vol. 7, no. 4, pp. 520–543, 1997.
[31] P. Z. Wieczorek, “An FPGA Implementation of the Resolve Time-Based True Random Number Generator With Quality Control,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 12, pp. 3450–3459, 2014.
[32] M. A. Zidan, A. G. Radwan, and K. N. Salama, “Random Number Generation Based on Digital Differential Chaos,” in 2011 IEEE 54th international midwest symposium on circuits and systems (MWSCAS). IEEE, 2011, pp. 1–4.
[33] Xilinx, “Xilinx virtex-7 fpga vc707 evaluation kit.” [Online]. Available: https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html
[34] R. Della Sala, D. Bellizia, and G. Scotti, “High-Throughput FPGA-Compatible TRNG Architecture Exploiting Multistimuli Metastable Cells,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 12, pp. 4886–4897, 2022.
[35] J. Chen, Z. Zhang, H. Lu, J. Hu, and G. E. Sobelman, “An Intra-Iterative Interference Cancellation Detector for Large-Scale MIMO Communications Based on Convex Optimization,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 11, pp. 2062–2072, 2016.
[36] Xilinx, “7 series fpgas data sheet: Overview, ds180 (v2.6.1).” September 8, 2020. [Online]. Available: https://docs.xilinx.com/v/u/en-US/ds180 7Series Overview
[37] S. Srinivasan, S. Mathew, V. Erraguntla, and R. Krishnamurthy, “A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS,” in 2009 22nd International Conference on VLSI Design. IEEE, 2009, pp. 301–306.
[38] S. K. Mathew, S. Srinivasan, M. A. Anders, H. Kaul, S. K. Hsu, F. Sheikh, A. Agarwal, S. Satpathy, and R. K. Krishnamurthy, “2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors,” IEEE Journal of Solid-State Circuits, vol. 47, no. 11, pp. 2807–2821, 2012.
[39] F. Cao and S. Li, “A Double-Scroll Based True Random Number Generator with Power and Throughput Adjustable,” in 2009 IEEE 8th International Conference on ASIC. IEEE, 2009, pp. 309–312.
[40] M. Bucci, L. Germani, R. Luzzi, P. Tommasino, A. Trifiletti, and M. Varanonuovo, “A High-Speed IC Random-Number Source for SmartCard Microcontrollers,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 50, no. 11, pp. 1373–1380, 2003.
[41] X. Wang, F. Liang, P. Miao, Y. Qian, and G. Jin, “10-Gbps True RandomNumber GeneratorAccomplished in ASIC,” in 2016 IEEE-NPSS Real Time Conference (RT). IEEE, 2016, pp. 1–4.
[42] Z. Tong, Y. Ming-yan, and Y. Yi-zheng, “Design of A Switched-current High-speed Truly Random Number Generator,” in 2005 6th International Conference on ASIC, vol. 1. IEEE, 2005, pp. 651–655.
[43] S.-G. Bae, Y. Kim, Y. Park, and C. Kim, “3-Gb/s High-Speed True Random Number Generator Using Common-Mode Operating Comparator and Sampling Uncertainty of D Flip-Flop,” IEEE Journal of Solid-State Circuits, vol. 52, no. 2, pp. 605–610, 2016.
[44] Y. Luo,W.Wang, S. Best, Y.Wang, and X. Xu, “A High-Performance and Secure TRNG Based on Chaotic Cellular Automata Topology,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 12, pp. 4970–4983, 2020.
[45] Z. Dai, A. Wolf, P.-P. Ley, T. Gl¨uck, M. C. Sundermeier, and R. Lachmayer, “Requirements for Automotive LiDAR Systems,” Sensors, vol. 22, no. 19, p. 7532, 2022.
[46] H.-G. Jeon, J. Park, G. Choe, J. Park, Y. Bok, Y.-W. Tai, and I. So Kweon, “Accurate Depth Map Estimation from a Lenslet Light Field Camera,” in Proceedings of the IEEE conference on computer vision and pattern recognition, 2015, pp. 1547–1555.
[47] D. Scharstein and R. Szeliski, “High-Accuracy Stereo Depth Maps Using Structured Light,” in 2003 IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 2003. Proceedings., vol. 1. IEEE, 2003, pp. I–I.
[48] S. B. Gokturk, H. Yalcin, and C. Bamji, “A Time-Of-Flight Depth Sensor – System Description, Issues and Solutions,” in 2004 conference on computer vision and pattern recognition workshop. IEEE, 2004, pp. 35–35.
[49] B. M. Al Bayati, A. K. Ahmad, and K. A. Al Naimee, “Influence of optical feedback strength and semiconductor laser coherence on chaos communications,” JOSA B, vol. 35, no. 4, pp. 918–925, 2018.