本論文提出一個使用電荷注入單元類比數位轉換器(Charge-Injection-Cell Analog-to-Digital Converter)的無須動態元件匹配(Dynamic Element Matching)二階多位元離散時間三角積分調變器(Delta-Sigma Modulator)。
作為多位元三角積分調變器，採用多位元量化器(Multi-Bit Quantizer)與數位類比轉換器(Digital-to-Analog Converter)的動態元件匹配一直是必須處理的議題，因此本論文提出一種可重複使用之電荷注入電路的架構，藉由重複使用相同的單位電容與反饋電容，以此達成多位元量化器、數位類比轉換器的目的，同時消除類比數位轉換器電容陣列不匹配與數位類比轉換器對動態元件匹配的需求。
為驗證此架構，本電路之晶片採用 40 奈米 1P9M 互補式金氧半導體製程製作，在 0.9/2.5 伏特電源電壓及 4.8 兆赫茲取樣頻率操作下，本架構可達到 SNDR為 80 dB，對應之 ENOB 為 12.9-bit，其功耗為 327 微瓦特，換算之能源效率指標(Figure of Merit) FOMS 為 158.8 dB，FOMW為 0.81 pJ/lev。

Abstract
This thesis presents a Dynamic Element Matching (DEM)-Free Second-Order Multi-Bit Discrete-Time Delta-Sigma Modulator with Charge-Injection-Cell Analog-to-Digital Converter (ADC).
As a multi-bit Delta-Sigma Modulator (DSM), the use of the multi-bit quantizer and the digital-to-analog converter (DAC) requires dealing with the issue of dynamic element matching (DEM). Therefore, this thesis proposes a reusable charge injection circuit architecture to achieve the purposes of the multi-bit quantizer and DAC, while eliminating the need for dynamic element matching.
The prototype is fabricated in 40nm 1P9M CMOS technology. At 0.9V/2.5V supply voltage and 4.8MS/s sampling rate, the proposed ADC achieves SNDR 80dB and corresponding ENOB 12.8-bit with consumes 327 μW power, resulting figure of merit (FoM) FOMS 158.8 dB and FOMW 0.81 pJ/lev.

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