此論文致力於改善高對地解析度衛星遙測應用訊雜比不足之問題並且提出兩個基於相鄰像素訊號傳遞時間延遲積分架構之影像感測器以提高訊雜比及驗證架構可行性。此架構不需額外像素內元件及複雜的金屬繞線並達到仿電荷耦合元件(CCD)之訊號傳輸功能但有著訊號範圍抑制及累加效率之問題。因此，本論文針對此架構之非理想效應進行改善
我們設計了陣列為 128 x 16之基於相鄰像素訊號傳遞時間延遲積分架構之影像感測器，其畫素大小為6 x 6 um2、填充因子為26.99%、感光度為0.976V/lux*s，並以TSMC 0.18μm 1P6M CIS製程製作。此晶片透過額外的像素內dummy電晶體設計減少在傳輸時開關耦合所造成之影響並在有限的訊號範圍實現更多的時間延遲級數;採用交錯的像素陣列設計以實施線性內插功能使得影像解析度提高為兩倍。在3.3伏特的操作電壓之下透過量測來驗證所提出之電路的功能以及效能。量測驗證的結果為: 在16個時間延遲積分級數操作以及在186 mW/m2平均光強度下有著15.27dB訊雜比之改善，整體電路操作頻率為3300張的每秒顯示幀數。
根據量測結果提出了陣列為1024x64之改良型時間延遲積分架構之影像感測器，其畫素大小為5x 5 um2、填充因子為52%，並以TSMC 0.18μm 1P6M CIS製程製作。此晶片採用背部照光製程有效地提高感光度3.527 V/lux*s;利用外部可調變之dummy電壓來調整適當的操作區間以求較佳的時間延遲積分效能。在3.3伏特的操作電壓之下透過量測來驗證所提出之電路的功能以及效能。量測驗證的結果為: 在10個時間延遲積分級數操作以及在186 mW/m2平均光強度下有著14.26dB訊雜比之改善，整體電路操作頻率為6600張的每秒顯示幀數。此晶片達到 65.97 V/V之訊雜比並符合設計規格。

This thesis is dedicated to improving signal-to-noise ratio issue in satellite remote sensing application for high ground resolution and presents two TDI prototypes based on APST methodology to increase SNR and verify feasibility. This structure achieves CCD-like transfer function without additional in-pixel device and complex routing effort but has swing degradation and addition efficiency issues. And the thesis concentrates on improving weakness of adopted structure.
A 128x16 APST-Based TDI sensor has been designed and fabricated in TSMC0.18μm 1P6M CIS technology with 6x6 um2 pixel size, 26.99% fill factor, 0.976V/lux*s light sensitivity. The extra dummy transistor is added in pixel design to reduce switch coupling during transfer and helps to implement more TDI stage in limited swing. The interlaced pixel array is adopted to implement linear interpolation for enhancing image resolution to double. The TDI functions and performance have been verified by experimental measurements at 3.3V supply voltage. The prototype achieves 15.27db SNR improvement with 16-stage operation under 186mW/m2 light irradiance at 3300 frame rate.
Revised TDI imager with 1024x64 pixel array has been designed and fabricated in TSMC 0.11um 1P4M CIS BSI technology. The pixel size is 5x5um2 with 52% fill factor. Thanks to BSI technology, the pixel sensitivity is enhanced to 3.527 V/lux*s. Tunable dummy voltage is adopted to select appropriate operation region for TDI performance. The TDI functions and performance have been verified by experimental measurements at 3.3V supply voltage. The chip achieves 14.26db SNR improvement with 10-stage operation under 186mW/m2 light irradiance at 6600 frame rate. The peak SNR reaches 65.97 V/V which matches design specification

[1] National Space Organization, National Applied Research Laboratories
[online] available: http://www.nspo.org.tw/tw/
[2] Thompson, L.L.; McCann, D.H.; Tracy, R.A.; Kub, F.J.; White, M.H., "Time-Delay-and-Integration Charge-Coupled Devices Using Tin Oxide Gate Technology," IEEE Journal of Solid-State Circuits, vol.13, no.1, pp.58,60, Feb 1978
[3] Schlig, E.S., "A TDI charge-coupled imaging device for page scanning," IEEE Journal of Solid-State Circuits, vol.21, no.1, pp.182,186, Feb 1986
[4] H.S. Wong, Y. L. Yao, and E. S. Schlig, “TDI charge-coupled devices: Design and applications,” IBM J. Res. Develop. 1992, vol. 36, no. 1, pp. 83–105, Jan..
[5] Agwani, S.; Miller, J. ; Chamberlain, S.G.; Washkurak, W.D., "High resolution tri-linear colour TDI CCD image sensor with programmable responsivity gain," Electron Devices Meeting, 1995.pp. 151-154
[6] J. Lu, Y. Liu, R. Liu, R. Vu, "The application of TDI-CCD in dental panoramic X-ray radiography," IEEE International Conference on Computer Science and Automation Engineering (CSAE), vol.2, no., pp.800,803, May 2012
[7] E. Fossum, “Active pixel sensors: Are ccd’s dinosaurs?” in Proc. SPIE Charged-Coupled Devices and Solid State Optical Sensors III, vol. 1900, pp. 30–39, 1993.
[8] K. Yonemoto, “Fundamentals and Applications of CCD/CMOS Image Sensors,” Q Pub. Co., Ltd., Tokyo, Japan, 2003. In Japanese.
[9] J.E. Carnes,W.F. Kosonocky, “Noise source in charge-coupled devices,” RCA Review, June 1972, 33(2), pp. 327–343.
[10] J. Ohta, Smart CMOS Imager Sensors and Applications, CRC Press
[11] Fu-Kai Tsai, Hong-Yi Huang, Li-Kuo Dai, Cheng-Der Chiang, Ping-Kuo Weng, Yung-Chung Chin, “A time-delay-integration CMOS readout circuit for IR scanning,” in Proc. 9th Int. Conf. Electron., Circuits Syst., 2002,vol. 1, pp. 347-350
[12] C.B. Kim, C.H. Hwang, B.H. Kim, Y.S. Lee, H.C. Lee, ” CMOS TDI readout circuit that improves SNR for satellite IR applications,” Electronics Letters, 2008, vol.44, pp.346-347
[13] C.B. Kim, B.K Kim, Y.S. Lee, H. Ju , H.C. Lee, “Smart CMOS Charge Transfer Readout Circuit for Time Delay and Integration Arrays,” in Proc. IEEE Custom Integr. Circuits Conf., 2006, pp.651-654.
[14] B.Tyrrell, K. et al.,"Time Delay Integration and In-Pixel Spatiotemporal Filtering Using a Nanoscale Digital CMOS Focal Plane Readout," IEEE Transactions on Electron Devices, vol.56, no.11, pp.2516,2523, Nov. 2009
[15] K.M. Nie, S.Y. Yao, J.T. Xu, J. Gao, "Thirty Two-Stage CMOS TDI Image Sensor With On-Chip Analog Accumulator," IEEE Trans. on VLSI Systems, , vol.22, no.4, pp.951-956, April 2014
[16] K.M. Nie, S.Y. Yao, J.T. Xu, J. Gao, Y. Xia, "A 128-Stage Analog Accumulator for CMOS TDI Image Sensor," IEEE Trans. on Circuits and Systems, vol.61, no.7, pp.1952,1961, July 2014
[17] G. Lepage, D. Dantès, W. Diels, “CMOS long linear array for space application,” in Proc. Electron. Imag. Conf.,vol. 6068, pp. 61–68, Jan. 2006.
[18] L. Wengao, G. Jun, C. Zhongiian, L. Jing, C. Wentao, T. Ju, and J. Lijiu,“A novel low-power readout structure for TDI ROIC,” in Proc. 5th Int. Conf. ASIC, 2003, vol. 1, pp. 591–594.
[19] Y. Hang, Q. Xinyuan, S.S. Chen; K.S. Low, "A Time-Delay-Integration CMOS image sensor with pipelined charge transfer architecture," IEEE International Symposium on Circuits and Systems (ISCAS), pp.1624,1627, May 2012
[20] K. W. Cheng, C. Yin, C. C. Hsieh, W. H. Chang, H. H. Tsai, and C. F. Chiu, “Time-delay integration readout with adjacent pixel signal transfer for CMOS image sensor,” International Symposium on VLSI-DAT, pp. 1-4, 2012.
[21] J. H. Chang, K. W. Cheng, C. C. Hsieh, W. H. Chang, H. H. Tsai, and C. F. Chiu, “Linear CMOS image sensor with time-delay integration and interlaced super resolution pixel,” in Proc. IEEE Sensors, pp. 1–4, October 2012.
[22] I. M. Hafez, G. Ghibauso, F. Balestra, “A study of flicker noise in MOS transistors operated at room and liquid helium temperatures,” Solid State Electronics, 1990,pp. 1525-1529.
[23] W. V. Backensto, C. R. Viswananathan, “Bias-dependent 1/f noise model of an MOS transistor,” IEEE Trans. Electron Devices, 1980, pp.87-92.
[24] J. F. Johnson, “Hybrid infrared focal plane signal and noise model,” IEEE Trans. Electron Devices, 1999, pp.96-108
[25] Xiqu Chen, “The noise analysis and its suppression in CMOS ROIC for microbolometric infrared focal plane array,” in Proc. SPIE, November 2008, vol. 7135 713539-8
[26] C. K. Liu, X. H. Yuan, X. H. Zhang, “Fixed pattern noise and its suppression in CMOS ROIC,” Semiconductor Optoelectronics, 2002, pp.170-173.
[27] Orly Yadid-Pecht, Ralph Etienne-Cummings, “CMOS Imagers from Phototransduction to Image Processing,” KLUWER ACADEMIC PUBLISHERS, 2004
[28] G. Lepage, J. Bogaerts, G. Meynants, “Time-Delay-Integration Architectures in CMOS Image Sensors,” IEEE Trans. Electron Devices, Nov. 2009,vol. 56, pp. 2524-2533.
[29] C. Liu, J. Lin, M. Tseng, “Design of CMOS sensor fill factor for optimal MTF and SNR,” Proc. of SPIE, 2010, Vol. 7826 78261N-1.
[30] S.M.A. Shah, "Simulation of dynamic MTF calibration system for an Earth observation satellite," Proceedings of 2nd International Conference on Recent Advances in Space Technologies,, pp.195,200, 9-11 June 2005
[31] F. Turk et al., "Design of a 4m resolution satellite imager for small satellites," Proceedings of 6th International Conference on Recent Advances in Space Technologies , pp.687,691, 12-14 June 2013
[32] J. F. Johnson, “Modeling imager deterministic and statistical modulation transfer functions,” Appl. Opt. ,Nov. 1993, vol. 32, no. 32, pp. 6503–6513.
[33] M. Sakakibara et al., "An 83dB-dynamic-range single-exposure global-shutter CMOS image sensor with in-pixel dual storage," IEEE International Solid-State Circuits Conference, pp.380,382, Feb. 2012
[34] G.Wan, Xiangli Li, G. Agranov, M. Levoy, M Horowitz, "CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography," IEEE Journal of Solid-State Circuits, vol.47, no.4, pp.1031,1042, April 2012
[35] K. Yasutomi, S. Itoh, S. Kawahito , "A Two-Stage Charge Transfer Active Pixel CMOS Image Sensor With Low-Noise Global Shuttering and a Dual-Shuttering Mode," IEEE Transactions on Electron Devices, vol.58, no.3, pp.740,747, March 2011
[36] [online] available: http://en.wikipedia.org/wiki/Stepper
[37] L. Yao, “CMOS readout circuit design for infrared image sensors,” in Proc. SPIE, 2009, Vol. 7384 73841B-1
[38] C. C. Hsieh, C. Y. Wu, F. W. Jih, T. P. Sun, “Focal-Plane Arrays and CMOS Readout Techniques of Infrared Imaging Systems,” IEEE Trans. on Circuits and Systems for Video Tech., 1997, Vol. 7, No. 4, pp. 594-605
[39] C.C. Hsieh et al, “High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA,” Solid-State Circuits,, August 1998, vol. 33, no. 8, pp. 1188--1198
[40] L.W. Huang, C.C. Hsieh. W.H. Chang, C.F. Chiu, "A 1.8V readout integrated circuit with adaptive transimpedance control amplifier for IR Focal Plane Arrays," in Proc. IEEE Sensors pp.1145,1148, Oct. 2011
[41] Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2000
[42] Dhruv Mahajan, Fu-Chung Huang, Wojciech Matusik, Ravi Ramamoorthi, Peter Belhumeur. “Moving Gradients: A Path-Based Method for Plausible Image Interpolation,” ACM Transactions on Graphics. 28(3) 2009.
[43] Bilinear interpolation, 28 September 2014
[online] available: http://en.wikipedia.org/wiki/Bilinear_interpolation
[44] C. Eichenberger, W. Guggenbuhl, "On charge injection in analog MOS switches and dummy switch compensation techniques," IEEE Trans. on Circuits and Systems, vol.37, no.2, pp.256,264, Feb 1990
[45] An Objective Look at FSI and BSI
[online] available:http://www.aptina.com/news/FSI-BSI-WhitePaper.pdf
[46] H. H. Chen, C. C. Hsieh, “An inverter-based capacitive trans-impedance amplifier readout with offset cancellation and temporal noise reduction for IR focal plane array,” International Symposium on Photoelectonic Detection and Image, vol. 8907, 2013.