此篇論文提出了一個適用於2.5-D IC中介層連接線的測試和修復方法。此方法的核心技術為脈衝消失測試技術(簡稱 PV-test)。此方法是藉由兩個主要電路：發射電路細胞和接收電路細胞來完成。發射電路細胞功能是發射一個短脈衝的脈衝進入中介層連接線，而接受電路細胞則負責在中介層連接線的輸出端判別是否有脈衝抵達。由於中介層連接線的負載效應，一個脈衝在經過了中介層連接線之後會有較長的上升時間和下降時間。我們可以藉由判別接收端是否有偵測到脈衝，來判別中介層連接線的延遲錯誤。脈衝消失測試方法不但可以偵測中介層連接線的開路故障也可以偵測中介層連接線之間的橋接故障，藉由在發射電路細胞中增加一個D型正反器讓每個測試週期只有一個脈衝輸入一條中介層連接線來測試橋接故障。此外，透過縮小測試模式下的驅動強度，此方法也可以偵測中介層連接線中較小的延遲錯誤。相較於其它中介層連接線測試方法，此方法有許多優點：因為此方法是由邏輯電路組成所以相當容易和傳統的邊界掃瞄電路合併；此方法的測試時間較短，我們只需要0.82毫秒來測試1024條中介層連接線；此方法支援即時診斷，我們可以利用診斷的結果，來實做內建自我修復機制讓整篇論文更加完整。

We present a general at-speed test method for die-to-die interconnects and demonstrate its particular application for the interposer wires in a 2.5-D IC. At the heart of this method is a Pulse-Vanishing test technique (called PV-test), in which a short-duration pulse signal is applied to an interposer wire under test at the driver end. If this pulse vanishes at the receiver’s output, then it indicates the presence of a delay fault. This PV-test technique is effective for detecting not only resistive open faults, but also resistive bridging faults between interposer wires. This method has several other advantages. For example, the implementation is especially easy as it incorporates only logic cells and can be merged with boundary scan cells. Besides, because it can support on-the-spot diagnosis, we already have implemented Built-In Self-Repair to make the whole thesis more solid.

[1] P. Y. Chen, C. W. Wu, and D. M. Kwai, “On-Chip TSV Testing for 3D-IC Before Bonding Using Sense Amplification,” Proc. of IEEE Asian Test Symposium, pp. 450-455, Nov. 2009.
[2] P. Y. Chen, C. W. Wu, D. M. Kwai, “On-Chip Testing of Blind and Open-Sleeve TSVs for 3D IC before Bonding,” IEEE Proc. of VLSI Test Symp., pp. 263-268, April 2010.
[3] C.-C. Chi, E. J. Marinissen, S. K. Goel, and C.-W. Wu, “Post-Bond testing of 2.5D-SICs and 3D-SICs Containing a Passive Silicon Interposer Base,” Proc. of Int’l Test Conf., pp. 1-10, 2011.
[4] M. Cho, C. Liu, D. H. Kim, S. K. Lim, and S. Mukhopadhyay, “Pre-Bond and Post-Bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3-D System,” IEEE Trans. on Components Packaging and Manufacturing Technology, Vol. 1, No. 11, Nov. 2011.
[5] K. Chakrabarty, “TSV Defects and TSV-Induced Circuit Failures: The Third Dimension in Test and Design-for-Test”, Proc. of Int’l Reliability Physics Symp., (IRPS), pp. 5F1.1-5F.1.12, 2012.
[6] Y. J. Huang, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A Built-In Self-Test Scheme for the Post-Bond Test of TSVs in 3D ICs,” Proc. of IEEE VLSI Test Symp, pp. 20-25, 2011.
[7] H. Lee and K. Chakrabarty, “Test Challenges for 3-D Integrated Circuits,” IEEE Design and Test of Computers, Vol. 25, No. 5, pp. 26-35, Sept.-Oct. 2009.
[8] Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, W.-T. Cheng, S. Sunter, Y.-F. Chou, and D.-M. Kwai, “Small Delay Testing for TSVs in 3D ICs,” IEEE Proc. of Design Automation Conf., June 2012.
[9] Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, and W.-T. Cheng, "Programmable Leakage Test and Binning for TSVs", Proc. of IEEE Asian Test Symp. (ATS), pp. 43-48, Nov. 2012.
[10] S.-Y. Huang, L.-R. Huang, K.-H. (Hans) Tsai, and W.-T. Cheng, "Delay Testing and Characterization of Post-Bond Interposer Wires in 2.5-D ICs", Proc. of Int'l Test Conf. (ITC), Sept. 2013.
[11] E. J. Marinissen, C.-C. Chi, J. Verbree, and M. Konijnenburg, “3D DfT Architecture for Pre-Bond and Post-Bond Testing,” Proc. of 3D Systems Integration Conf., pp. 1-8, 2010.
[12] E. J. Marinissen, “Challenges and Emerging Solutions in Testing TSV-Based 2.5-D and 3D-Stacked ICs,” Proc. of IEEE Design, Automation, and Test in Europe Conf., pp. 1277-1282, 2012.
[13] B. Nadeau-Dostie, J. F. Cote, H. Hulvershorn, and S. Pateras, “An Embedded Technique for At-Speed Interconnect Testing”, Proc. of IEEE Int’l Test Conf., pp. 431-438, 1999.
[14] B. Noia and K. Chakrabarty, “Pre-bond probing of TSVs in 3D Stacked ICs,” Proc. of Int’l Test Conf., pp. 1-10, 2011.
[15] B. Noia, K. Chakrabarty, and E. J. Marinissen, “Optimization Methods for Post-Bond Die-Internal/External Testing in 3D Stacked ICs”, Proc. of Int’l Test Conf., pp. 1-10, Nov. 2010.
[16] P. R. O’Brien and T. L. Savarino, “Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation,” Proc. of Design Automation Conf., pp. 512–515, Nov. 1989.
[17] R. Pendurkar, A. Chatterjee, Y. Zorian, "Switching Activity Generation with Automated BIST Synthesis for Performance Testing of Interconnects", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 9. pp. 1143-1158, Sept. 2001.
[18] F. Ye and K. Chakrabarty, “TSV Open Defects in 3D Integrated Circuits: Characterization, Test, and Optimal Spare Allocation”, Proc. of Design Automation Conf., pp. 10240-1030, June 2012.
[19] IEEE Computer Society, “IEEE Std 1149.1TM-2001, IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE, June, 2001.
[20] “CIC Reference Flow for Cell-based IC Design”, Chip Implementation Center, CIC, Taiwan, Document no. CIC-DSD-RD-08-01, 2008.