隨著科技日新月異地進步，數位微流體生物晶片已經逐漸地取代傳統生物實驗的實驗平台。藉著將生物實驗流當中所需的功能整合，數位微流體生物晶片可以降低人為的介入以及提高整體實驗的可自動化程度。而基於數位微流體生物晶片架構的新興晶片於近期被發表，名為微電極點陣列架構下之數位微流體生物晶片。與傳統的微流體生物晶片相比，微電極點陣列架構下之數位微流體生物晶片的每個微電極上都有感測裝置，而在傳統的微流體生物晶片上，感策裝置則是被設置在特定的位置。有了這個優勢，將有利於在微電極點陣列架構下之數位微流體生物晶片上實行即時的生物實驗偵測。然而，就我們所知，以往的生物實驗合成演算法並未在微電極點陣列架構下之數位微流體生物晶片上考慮生物實驗的不確定性，以至於即時偵測的性質並沒有被完全的發揮。在生物實驗進行當中，有些生物實驗步驟會因為生物實驗的不確定性而提早完成或是延後。如此的不確定因素將會對設計生物實驗合成之模組佈局演算法時造成影響，模組佈局乃為將生物實驗的每個步驟給予一個相對應的生物實驗模組，該實驗模組會被擺放在生物晶片上並執行所賦予的生物步驟。在這篇論文中，我們提出了第一篇在微電極點陣列架構下之數位微流體生物晶片上考慮生物不確定性之模組佈局演算法，透過我們的演算法，在考慮生物實驗不確定的情況下，整體的生物實驗執行時間將可被縮短，再者，在不超過比較對象的執行時間前提之下，我們亦能縮小生物實驗所需的晶片大小。

Digital microfluidic biochips (DMFBs) are an emerging technology that are replacing traditional laboratory procedures. With the integrated functions which are necessary for biochemical experiments, DMFBs are able to achieve automatic experiments. Recently, DMFBs based on a new architecture called micro-electrode-dot-array (MEDA) have been demonstrated. Compared with conventional DMFBs which sensors are specifically located, each microelectrode is integrated with a sensor on MEDA-based biochips. Benefiting from the advantage of MEDA-based biochips, real-time reaction-outcome detection is attainable. However, to the best of our knowledge, synthesis algorithms proposed in the literature for MEDA-based biochips do not fully utilize the real-time detection since completion-time uncertainties have not yet been considered. During the execution of a biochemical experi- ment, operations may finish earlier or delay due to variability and randomness in biochemi- cal reactions. Such uncertainties also have e↵ects when allocating modules for each fluidic operation and placing them on a biochip since a biochip with a fixed size area restricts the number and size of these modules. Thus, in this thesis, we proposed the first operation- variation-aware placement algorithm not only takes completion-time uncertainties into ac- count but also exploits real-time detection on MEDA-based biochips. Simulation results demonstrate that with the proposed approach, it leads to reduced time-to-result and mini- mizes the chip size while not exceeding completion time compared to the benchmarks.

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