應用於克勞斯網路的增進固定非同步式的分配機制

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研究生：	趙哲希 Chao, Che-Hsi
論文名稱：	應用於克勞斯網路的增進固定非同步式的分配機制 Improved Static Desynchronization Dispatching Scheme for Clos-Network Switches
指導教授：	許雅三 Hsu, Yarsun
口試委員:	鐘太郎闕河鳴
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2012
畢業學年度：	100
語文別：	中文
論文頁數：	51
中文關鍵詞：	克勞斯網路
相關次數：	點閱：3 下載：0
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三級式克勞斯網路已為大眾所認可的可擴張式網路機制，而分散式分配路徑的克勞斯網路已被大量提出。目前已提出的分配機制讓每條路徑達到很高處理效能。但使用加速讀取的記憶體，以及分配的演算法，使得系統難以實現。首先，這篇論文介紹一個不使用加速讀取的新架構。之後，此論文提出兩個演算法較容易實現，的分配機制。第一個提出的機制十分簡易，也就是固定非同步連接機制(Static Desynchronization scheme)。此機制以非同步的方式，來避免資源竸爭，並以增加通道的使用率。當資料欲到達所有輸出埠的機率都相同時，此機制能用很短的分配路徑時間來達成100%的處理效能。第二個提出的機制是用來改善固定非同步連接機制較不彈性的缺點，也就是改善固定非同步連接機制(Improved Static Desynchronization scheme)。我們將使用固定非同步效能為基礎，並另增加有彈性的分配路徑機制。除此之外，我們提出指定優先順序的方式，使新增加的機制也達到非同步，降低同時競爭相同資源的機率。我們將呈現如何改利用非同步化的效用以減少在第二級競爭同一輸出通道的機率來達到在任何交通模式中皆可以達到100%的處理效能。

Chapter 1    Introduction    1
1    Motivation    1
2    Goal    2
3    Thesis Organization    3
Chapter 2    Related Work    4
1    Space-Space-Space Clos-Network    4
2    Memory-Space-Memory Clos-Network    5
3    Summary    6
Chapter 3    Architecture    7
1    Input Module Architecture    7
2    Output Module Architecture    8
3    Architecture of MSM    12
4    Summary    12
Chapter 4    The Introduction of Static Desynchronization    14
1    Random Dispatching Scheme    14
2    Desynchronization Effect    16
3    Static Desynchronization Dispatching Scheme    18
Chapter 5    The Introduction of Improved Static Desynchronization    23
1    Drawback of Static Desynchronization    23
2    Improved Static Desynchronization Scheme    24
3    The Desynchronized Pointers    30
Chapter 6    Performance Evaluation    34
1    Evaluation Methodology    34
2    Performance on Uniform Traffic Pattern    35
3    Performance on Non-Uniform Traffic Pattern    37
Chapter 7    Implementation    41
1    Dispatching Scheduling Time    41
2    Hardware Complexity    42
3    Interconnection Wire Complexity    43
4    Comparison of Implementation Complexity and Synthesis Result    45
Chapter 8    Conclusions and Future Work    47
1    Conclusions    47
2    Future Work    47
Bibliography    49

                                

[1] N. McKeown, “The iSLIP scheduling algorithm for input-queues switches,” IEEE/ACM Trans. Networking, vol. 7, pp. 188–200, Apr.1999.
[2] T. Anderson, S. Owicki, J. saxe, and C. Thacker, “High speed switch scheduling for local area networks,” ACM Transaction on Computer Systems, vol. 11, no. 4, pp. 319-352, November 1993.
[3] C. Clos, “A study of nonblocking switching networks,” Bell Syst. Tech. J., pp. 406-424, Mar. 1953.
[4] F.M. Chiussi, J.G. Kneuer and V.P. Kumar, “Low-cost scalable switching solutions for broadband networking: the ATLANTA architecture and chipset,” IEEE Communication Magazine, vol. 35, no.3, pp. 44-53, December 1997.
[5] E. Oki, Z. Jing, R. Rojas-Cessa, and J. chao, “Concurrent Round-Robin Based Dispatching Schemes for Clos-Network Switches , ” IEEE/ACM Trans. On Networking, pp. 830-844, Vol. 10, issue 6, Dec 2002.
[6] E. Oki, R. Rojas-Cessa, and H. J. Chao: “A pipeline-based approach for maximal-sized matching scheduling in input-buffered switches”, IEEE Communications Letters, vol. 5, no. 6, 2001, pp. 263-265, 2001.
[7] K. Pun and M. Hamdi, “Distro: A Distributed Static Round-Robin Scheduling Algorithm for Bufferless Clos-Network Switches,” IEEE GLOBECOM ’02, Taipei, Taiwan, Nov 17–21, 2002.
[8] R. Rojas-Cessa, and H. J. Chao: “Maximum Weight Matching Dispatching Scheme in Buffered Clos-Network Packet Switches”, in Proc. IEEE International Conference on Communications 2004 - ICC-2004, Paris, France, pp. 830-844, 2004.
[9] S. Iyer, N. McKeown: “Analysis of the parallel packet switch architecture”, IEEE/ACM Trans. on Networking, 2003, 314-324.
[10] P. Konghong, M. Hamdi, “Static Round-robin Dispatching Schemes for Clos-network Switches,” IEEE HPSR 2002, pp. 329-333, May 2002.
[11] C. Lin and R. Rojas-Cessa, “Module Matching Schemes for Input-Queued Clos-Network Packet Switches,” IEEE International Conference on Communications (ICC’08), 2008.
[12] H. J. Chao, Z. Jing, and S. Y. Liew, “Matching algorithms for three stage bufferless Clos-network switches,” IEEE Commun. Mag., vol. 41,no. 10, pp. 46-54, Oct. 2003
[13] Y. Jiang and M. Hamdi, “A fully desynchronized round-robin matching scheduler for a VOQ packet switch architecture,” IEEE Workshop on High Performance Switching and Routing, pp. 407-411 ,May 2001.

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