近年來，一種稱作相位訊號處理的影像處理技術被提出來，其原理為利用相位資訊來判斷位移，而非使用具有高度運算複雜的光流法。此技術已經被應於像是畫面內插，視點合成及影像放大等應用。相位訊號處理是建構在複數可控金字塔的影像分解及重建上。而演算法中的運算複雜度主要集中於在複數可控金字塔的分解及重建上。隨著解析度增加，隨之上升的運算複雜度將使即時運算的應用難以實現。在本篇論文中，我們將對於這項問題，提出高效的複數可控金字塔之硬體。

傳統的作法會採用快速傅立葉變換作為複數可控金字塔的實現方式，但此方式將使用大量的晶載記憶體及延遲緩衝器。此外，二維的快速傅立葉變換將消耗高頻寬的記憶體資源。針對這些問題，我們採取了基於有限脈衝響應的硬體實現。針對一維的複數可控金字塔，相較基於快速傅立葉變換的複數可控金字塔之硬體實現，我們的硬體減少68\%的邏輯閘及62\%的晶載記憶體。針對二維的複數可控金字塔，我們的目標是提出每秒60幀的全高清畫質的複數可控金字塔處理引擎。此設計的挑戰是二維的複數可控金字塔需要高頻寬的記憶體資源以及大量的晶載記憶體。我們提出基於條狀的運算流程來降低記憶體頻寬及節省85\%的晶載記憶體。

我們基於台積電40奈米製程實作我們的一維及二維複數可控金字塔之硬體。一維複數可控金字塔的電路使用483K的邏輯閘，以及85-KB的晶載記憶體。在250MHz下合成時，能夠時能提供吞吐量達314Mpixel/s來支援每秒30幀的4K超高畫質顯示器。二維複數可控金字塔的電路使用1.5M的邏輯閘，以及32-KB的晶載記憶體。在222MHz下合成時，能夠時能提供吞吐量達126Mpixel/s來支援每秒60幀的全高清畫質影片。此外，我們也將二維複數可控金字塔的電路實作在FPGA平台上，跑在80MHz之操作頻率下，提供每秒30張1024x1024解析度的影片。

In recent years, a novel video processing technique called phase-based processing was proposed. This method measures the motion by local phase instead of computationally-intensive optical flow, and it has been applied on various applications, such as frame interpolation, view synthesis, and video magnification. Phase-based processing is based on the complex steerable pyramid (CSP). However, the decomposition and reconstruction of CSP occupied the most of the computation complexity of phase-based algorithm. With the increasing of image resolution, the high computational complexity of CSP makes real-time application difficult. In this thesis, we aim to resolve this difficulty by providing detailed design analysis and efficient VLSI implementation for CSPs.

For hardware implementation, conventional method used the fast Fourier transform (FFT) for CSP implementation. However, the FFT needs large numbers of on-chip memory and delay buffers. Moreover, the 2D-FFT needs huge DRAM bandwidth. To address these problems, we adopt a computation- and memory-efficient finite impulse response (FIR) implementation. In 1-D CSP, we reduce 68\% of gate counts and 62\% of on-chip memory compared to FFT-based CSP. For 2-D CSP, we aim to introduce a FHD CSP processing engine at 60fps. The design challenge is that 2-D CSP requires high bandwidth and large size of on-chip memory. We propose a stripe-based computation flow to reduce the DRAM bandwidth and save 85\% of on-chip memory compared to frame-based computation flow.

We implemented both our 1-D and 2-D CSP VLSI circuit using TSMC 40nm technology process. The 1-D CSP circuit uses 483K gate count and 85KB on-chip memory. When synthesized at 250 MHz, it can deliver 314 Mpixel/s to support 4K Ultra-HD Display at 30fps. The 2-D CSP circuit uses 3.5M logic gates and 32KB on-chip memory. When synthesized at 222 MHz, it delivers 126 Mpixel/sec to support FHD Video at 60fps. Besides, we also implement our 2-D CSP on FPGA. The FPGA demo system operates at 80MHz and achieves real-time performance for 1024x1024 resolution video at 30 fps.

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