隨著快閃記憶體的需求快速增加，快閃記憶體的可靠性也越來越重要；利用快閃記憶體的非揮發性的特質，錯誤更正碼(Error Correcting Code)被廣泛的使用在快閃記憶體上。

在本論文中，我們針對快閃記憶體設計了BCH 碼(Bose-Chaudhuri-Hocquenghem)及低密度同位元編解碼 (Low-Density Parity-Check)，我們也建立了一個評估框架來評估分析不同錯誤更正碼的錯誤更正能力。我們設計了一個由BCH碼及LDPC所組成的混合編解碼，為了要最佳化混合編解碼，我們評估現有混合科技應用在快閃記憶體上的錯誤更正能力；關於快閃記憶體的限制，我們以實際上應用的面積及時間的需求為目標。考慮到實作成硬體，我們採用QC(Quasi-cyclic)-LDPC碼做為混合編解碼中的LDPC碼；經過分析的結果，我們採用Turbo-decoding message-passing (TDMP)演算法作為LDPC碼的解碼演算法。在分析完快閃記憶體系統之後，我們也針對我們的設計提出了硬體架構；最後將對於我們的與他人的硬體架構作了比較；在相同的硬體環境之下，我們的解碼器只需要相對於其他解碼器十分之一的記憶體，而且解碼器的效能仍滿足快閃記憶體的時間限制；結果顯示我們的混合編解碼較適合快閃記憶體的應用。

關於未來的展望，我們可以考慮採用歐幾里德幾何(EG)-LDPC碼，EG-LDPC碼對於多層單元快閃記憶體會有更好的錯誤更政能力；另外，編解碼器的硬體架構也還有改善的空間。

Flash memory, as its rapidly increasing demand recently, suffers from the reliability issue.
However, due to its non-volatile nature, error correcting codec (ECC) are widely adopted
for flash memory.
In this thesis, we design the error correcting codes, including low-density parity-check
(LDPC) and Bose-Chaudhuri-Hocquenghem (BCH) codes for flash memories. We also establish
an evaluation framework for the performance analysis among different ECCs. To
optimize the design parameters of the hybrid codes that integrate LDPC and BCH codes,
we evaluate the existing hybrid technologies for error correcting scheme of the non-volatile
memory. We target at the specification of a flash memory with realistic spare capacity
and timing requirement. Considering the practical hardware implementation, we design and
evaluate quasi-cyclic (QC) LDPC codes. The cyclic encoding and turbo-decoding messagepassing
(TDMP) algorithm are analyzed as the encoding and decoding algorithm. With the
evaluation result for the proposed flash memory system, the hardware architecture of the
encoder and decoder are also presented. Finally, the comparison of the proposed architecture
with other works is made. The memory usage of our decoder can be as low as 10%
of previous work, while the decoding cycle is within the specification of the flash memory
system. The result shows that our hybrid LDPC and ECC scheme is efficient for non-volatile
memory.
Our future work include the study of Euclidean geometric (EG) LDPC codes, the improvement
of the encoder and decoder architecture and the construction of specific error
model of dedicate the non-volatile memory.

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