隨著製程演進、半導體的進步，運用於現今無線通訊系統收發模塊(Transceiver)、數據及時鐘恢復電路(Clock and Data Recovery-CDR)、頻率合成器(Frequency synthesizer)、數位電視接收機等等之鎖相迴路(PLL)成為設計要點。在本論文中將對傳統鎖相迴路做探討，並經過數值分析、架構轉換，將傳統鎖相迴路轉換為全數位式鎖相迴路(All Digital Phase Lock Loop)，在新製程下之迴路設計達到較好的轉移。
本論文對於全數位式鎖相迴路系統架構做分析，在時間數位轉換器上採用閘控環型振盪器為基礎之轉換器，並解析其架構運作原理及表現，在架構內部運作上做探討，解決不理想效應之影響。全數位式鎖相迴路主要將傳統鎖相迴路濾波器之電容電阻轉換為數位電路型式，可降低晶片面積，另外數位電路對於新製程可達到較好的轉移。而在振盪器部分延用傳統LC tank振盪器，主要設計要點為其振盪頻率、相位雜訊以及消耗能量等，另外與傳統鎖相迴路相比，全數位式鎖相迴路振盪器前方將加入數位類比轉換器(DAC)做數值轉換。除頻器與傳統鎖相迴路架構相同，主要設計其除數演算，將頻率鎖定在所要頻率。隨著數位電路取代傳統類比電路，全數位式鎖相迴路的出現儼然成為現今研究的趨勢。

With the advancement of process development and semiconductors, it can be applied to transceivers, clock and data recovery (CDR), frequency synthesizers, digital television receivers, and so on in today's wireless communication systems that make Phase-locked loops (PLL) become the design emphasis. In this thesis, the traditional phase-locked loop will be discussed, and after numerical analysis and architecture conversion, the traditional phase-locked loop is converted into an all-digital phase-locked loop (ADPLL), and the circuit design under the new process is achieved a better transfer.
This dissertation analyzes the architecture of an all-digital phase-locked loop system and uses a gate-controlled oscillator as the basis for a time-to-digital converter, analyzes its operating principle and performance. It discusses the internal operation of the architecture and solve the non-ideal effects. The all-digital phase-locked loop mainly converts the capacitance and the resistance of the traditional PLL’s loop filter into a digital circuit type, which can reduce the area of the chip. In addition, the digital circuit can achieve better transfer under the new process. In the oscillator part, the oscillator structure is extended the traditional PLL’s. The main design points are its oscillation frequency, phase noise, and power consumption. Compared with the traditional phase-locked loop, the digital phase-locked loop oscillator will incorporate a digital to analog converter (DAC) in front of it to do numerical conversions. The frequency divider is the same as the traditional PLL. The divisor calculus is mainly designed to lock at the desired frequency. With the trend of digital circuits replacing analog circuits, the all-digital phase-locked loops has become a research trend.

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