在日常生活中，靜態隨機存取記憶體存在於各種電子產品中，且於各種電路及系統單晶片中占據了越來越多的面積。這代表了靜態隨機存取記憶體佔據了晶片中大量的功耗。所以，如何減少靜態隨機存取記憶體功耗而又不降低操作性能是一個相當大的挑戰。
要降低靜態隨機存取記憶體之功耗，降低操作電壓是一個有效的做法。但是降低操作電壓會使得靜態隨機存取記憶體面臨以下問題: (1) 讀取失真及半選擇失真 (2) 寫入能力及半選擇失真容忍之抵換 (3) 降低感測邊限造成的讀取錯誤跟低操作速度。過去的作品可以解決讀取失真的問題，但是都無法解決寫入能力及半選擇失真容忍之抵換，除非使用寫回的機制，但是寫回機制會耗去額外的時間跟功耗。以上的種種問題導致過去的作品無法於低壓下操作、並且有較好的操作速度。
在這個作品，我們提出了一具有雙重資料警覺寫入輔助及負壓讀取字元線之八電晶體靜態隨機存取記憶體。受惠於雙重資料警覺控制之: (1)資料警覺之記憶胞源極電壓 (2) 資料警覺之寫入字元線，這個行基的雙重資料警覺寫入輔助初次解決了寫入能力及行列上的半選擇失真容忍之抵換問題。負壓讀取字元線加大了讀取位元線之振福且改善了讀取速度。
透過六十五奈米互補式金氧半邏輯製程技術，建構出一容量為十六千字元之雙重資料警覺寫入輔助之八電晶體靜態隨機存取記憶體。藉由示波器以及測試機台PK2之量測，此晶片可於三百毫伏之操作電壓下以四十八百萬赫茲的頻率下運行且最低可達到兩百一十毫伏之操作電壓與七點三百萬赫茲之操作頻率。這個作品之品質因數: 記憶胞穩定性乘以操作頻率除以記憶胞面積乘以最低操作電壓為其他低操作電壓之靜態隨機存取記憶體之十四倍。 

In our livelihood, Static Random Access Memory (SRAM) appears in the almost electronics and it is required much more area than other circuits in the SoC chip. It shows the SRAM used the most power of a chip. So, how to solve the power consumption issue of SRAM and not to reduce the operating performance of SRAM is a big challenge.
To make the power consumption reduce for SRAM, lower operating voltage is an useful method. But SRAM operated at low VDD suffers the following: (1) read disturb and half-select disturb (2) write ability and half-select tolerance trade off, and (3) reduced sensing margin (SM) as well as read failure and slow speeds. Previous works achieved read-disturb-free operations; but do not solve the trade-off between the half-select tolerance and write ability without time-consuming and power-consuming write-back (WB) scheme. All of this issue makes previous work can’t operate at ultra low voltage with higher speed.
In this work, we proposes an 8T cell with dual data-aware write-assist (D2AW) and negative read word-line (NRWL) schemes. The column-based D2AW provides, for the first time, the solution to the trade-off between the row/column half-select (HS)-static noise margins (SNM) and the write margin (WM) thanks to the dual data-aware controls of: (1) cell-VSS (DA-CVSS) and (2) write word-line (DA-WWL). NRWL expands the RBL voltage swing and improve the read speed.
A fabricated 65nm CMOS logic process 128-row 16Kb D2AW8T SRAM achieved 7.3MHz/48MHz at VDD=210mV/300mV by oscilloscope and Personal Kalos 2 testing. The figure of merit (FOM): [cell stability (CS)*cycle frequency (f)]/[cell area (A)*minimum VDD (VDDmin)] is 14+x higher than that of other low-VDDmin SRAM cells.

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