使用具有製程、電壓、溫度不敏感性的電壓-時間-電壓轉換器之十三位元低過取樣速率五階雜訊塑形連續漸進式類比數位轉換器

簡易檢索 / 詳目顯示

回結果列表

研究生：	劉寶樹 Liu, Pao-Shu
論文名稱：	使用具有製程、電壓、溫度不敏感性的電壓-時間-電壓轉換器之十三位元低過取樣速率五階雜訊塑形連續漸進式類比數位轉換器 A 13-ENOB Low-OSR Fifth-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter
指導教授：	謝志成 Hsieh, Chih-Cheng
口試委員:	洪浩喬 Hong, Hao-Chiao 陳佳宏 Chen, Chia-Hung 李泰成 Lee, Tai-Cheng
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2023
畢業學年度：	112
語文別：	英文
論文頁數：	75
中文關鍵詞：	雜訊塑形、電壓-時間-電壓轉換器、製程、電壓、溫度不敏感性、連續漸進式類比數位轉換器
外文關鍵詞：	noise-shaping, V-T-V, PVT-insensitive, SAR
相關次數：	點閱：4 下載：3
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

這篇論文提出一顆十三位元低過取樣速率五階雜訊塑形連續漸進式(successive-approximation register, SAR)類比數位轉換器(analog-to-digital converter, ADC)。
關鍵的雜訊塑形過濾器(noise shaping filter)部分使用了改良過的電壓-時間-電壓(Voltage-Time-Voltage, V-T-V)轉換器提供了可靠的開環增益,由於此增益主要來自於兩顆不同電容與兩條不同電流之間的比例,其增益本質上對於製程、電壓與溫度(Process-Voltage-Temperature, PVT)具有不敏感性,因此並不需要額外的校正或修剪即可實現理想的雜訊轉換函數 (noise transfer function, NTF)。此外,V-T-V轉換器只消耗動態功率。透過使用元件比例設計與動態功耗方式,所提出的ADC具有抵抗PVT變異與良好功率效益的特性。本作更解決了原本電流雜訊的問題，將ADC的解析度上升到更高的位置。
為了驗證本電路,此架構使用40奈米1P10M互補式金氧半導體製程製作,核心電路面積為 590 x 100um2,在1.1伏特電源電壓及五百萬赫茲取樣頻率操作下,此晶片在625千赫茲輸入頻寬實現之SNDR為81.8dB,其對應的ENOB為13-bit,功率消耗為90微瓦,而等效的Walden figure of merit (FoMW)為7.2fJ/conversion-step,Schreier figureof merit (FoMS)為180.2dB。

This paper presents a 13-bit low oversampling rate 5th-order noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC). The key component of the noise-shaping filter utilizes a reliable open-loop gain Voltage-Time-Voltage (V-T-V) converter. The gain primarily stems from the ratio of two different capacitors and two distinct currents, making it inherently insensitive to Process-Voltage-Temperature (PVT) variations. As a result, no additional calibration or trimming is required to achieve the desired noise transfer function (NTF). Furthermore, the V-T-V converter operates with dynamic power consumption. By employing component ratio design and dynamic power approach, the proposed ADC exhibits resistance to PVT variations and excellent power efficiency. This work further addresses the issue of current noise, elevating the resolution of the ADC to a higher level.
To validate this circuit, the architecture was fabricated using a 40nm 1P10M CMOS process. The core circuit area is 590 x 100um2. Operating at a supply voltage of 1.1V and a sampling frequency of 5MHz, this chip achieves an SNDR of 81.8 dB with a 625 kHz input bandwidth. The ENOB is 13 bits, and the power consumption is 90uW. The equivalent Walden figure of merit (FoMW) is 7.2 fJ/conversion-step, and the Schreier figure of merit (FoMS) is 180.2 dB.

Key words : noise-shaping SAR, V-T-V converter, low OSR, 5th-order NTF, PVT insensitive

ABSTRACT    I
CONTENTS    IV
LIST OF FIGURES    VIII
LIST OF TABLES    XI
CHAPTER 1    INTRODUCTION    1
1    MOTIVATION    1
2    SELECTION OF ARCHITECTURE    1
3    THESIS ORGANIZATION    3
CHAPTER 2    FUNDAMENTALS OF ADC    4
1    NYQUIST THEOREM    4
2    RESOLUTION    5
3    OFFSET ERROR    5
4    GAIN ERROR    6
5    QUANTIZATION ERROR    7
6    SIGNAL-TO-NOISE RATIO (SNR) AND EFFECTIVE NUMBER OF BITS (ENOB)    9
7    SIGNAL-TO-NOISE AND DISTORTION RATIO (SNDR)    10
8    EFFECTIVE NUMBER OF BITS (ENOB)    10
9    DIFFERENTIAL NONLINEARITY (DNL)    11
10    INTEGRAL NONLINEARITY (INL)    12
11    SPURIOUS-FREE DYNAMIC RANGE (SFDR)    13
12    FIGURE OF MERIT (FOM)    13
CHAPTER 3    OVERVIEW OF ADCS    14
1    TOP-LEVEL DISCUSSIONS    14
1.1    SAR ADC    14
1.2    Sigma-Delta Modulator (DSM or SDM)    16
1.3    Noise Shaping SAR ADC    18
2    SAMPLE AND HOLD (S/H) CIRCUITS    20
2.1    Sampling Speed    20
2.2    Signal Dependent Resistance    21
2.3    Charge Injection    22
2.4    Clock Feedthrough    23
2.5  kT/C Noise ……………………………………………………………. .24
3    DIGITAL-TO-ANALOG CONVERTER USING CAPACITIVE ARRAY    25
3.1    Parasitic Capacitance    26
3.2    Mismatch    27
4    COMPARATOR    28
4.1    Input-referred offset    29
5    ASYNCHRONOUS SAR LOGIC    30
6    STRUCTURE OF NOISE SHAPING SAR ADC    31
6.1    Cascaded Integrator Feed-Forward    31
6.2    Error-Feedback    32
7    SUMMARY    33
CHAPTER 4    DESIGN CONSIDERATIONS OF NOISE SHAPING SAR ADC    35
1    DIFFERENTIAL ADC    36
2    SAMPLE AND HOLD    37
3    COMPARATOR    37
4    CDAC    38
5    IMPLEMENTATION OF RESIDUE PROCESS    40
5.1    Prior Art    40
5.2    Signal Model    43
5.3    Non-Ideal Effect    44
6    SUMMARY    46
CHAPTER 5    CIRCUIT IMPLEMENTATION OF PROPOSED NOISE        SHAPING SAR ADC    47
1    ARCHITECRURE OF PROPOSED NS SAR ADC    48
2    ARCHITECRURE OF PROPOSED V-T-V CONVERTER    50
3    DESIGN OF V-T-V CONVERTER AND SC FIR FILTERS    53
4    DESIGN OF SAMPLE AND HOLD (S/H)    54
5    DESIGN OF COMPARATOR    55
6    DESIGN OF CAPACITIVE DAC (C-DAC)    57
7    PRE-LAYOUT AND POST-LAYOUT SIMULATION    59
8    SUMMARY    61
CHAPTER 6    EXPERIMENTAL RESULTS    63
1    MEASUREMENT ENVIRONMENT SETUP    63
2    CHIP MICROGRAPH    64
3    MEASUREMENT RESULTS    65
4    PERFORMANCE COMPARISON    68
5    SUMMARY    68
CHAPTER 7  CONCLUSION    70
1    CONCLUSION    70
2    FUTURE WORK    70
BIBLIOGRAPHY    72

                                

[1] B. Murmann, "ADC Performance Survey 1997-2023," [Online]. Available:http://web.stanford.edu/~murmann/adcsurvey.html.
[2] W. Guo, H. Zhuang and N. Sun, "A 13b-ENOB 173dB-FoM 2nd-order NS SAR ADC with passive integrators," 2017 Symposium on VLSI Circuits, 2017, pp. C236-C237.
[3] L. Jie, B. Zheng, H.-W. Chen, and M. P. Flynn, “A cascaded noise-shaping SAR architecture for robust order extension,” IEEE J. Solid-State Circuits, vol. 55, no. 12, pp. 3236–3247, Dec. 2020.
[4] R. J. Baker, CMOS: Circuit Design, Layout, and Simulation, 3rd ed. WILEY, 2010.
[5] T.-H. Wang, R. Wu, V. Gupta, X. Tang, and S. Li, “A 13.8-ENOB fully dynamic third-order noise-shaping SAR ADC in a single-amplifier EF-CIFF structure with hardware-reusing kT/C noise cancellation,” IEEE J. Solid-State Circuits, vol. 56, no. 12, pp. 3668–3680, Dec. 2021.
[6] J. Liu, D. Li, Y. Zhong, X. Tang, and N. Sun, “A 250 kHz-BW 93 dB-SNDR 4th-order noise-shaping SAR using capacitor stacking and dynamic buffering,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), Feb. 2021, pp. 369–371.
[7] T. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, 2nd ed. WILEY, 2012.
[8] R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Select. Areas Commun, vol. 17, no. 4, pp. 539–550, Apr 1999.
[9] R. Schreier and G. C. Temes, "Understanding Delta-Sigma Data Converters," IEEE Press, 2005.
[10] B. Razavi, Design of Analog CMOS Integrated Circuits, 1st ed.: McGraw-Hill 2002.
[11] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink and B. Nauta, "A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC," in IEEE ISSCC Dig. Tech. Papers, pp. 244-610, Feb. 2008.
[12] P. M. Figueiredo and J. C. Vital, "Kickback noise reduction techniques for CMOS latched comparators," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 7, pp. 541-545, July 2006.
[13] C. Liu, S. Chang, G. Huang and Y. Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010.
[14] T. Wang, T. Xie, Z. Liu, and S. Li, “An 84 dB-SNDR low-OSR 4th-order noise-shaping SAR with an FIA-assisted EF-CRFF structure and noise-mitigated push-pull Buffer-in-Loop technique,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2022, pp. 418–420.
[15] Y. Lin, C. Lin, S. Tsou, C. Tsai and C. Lu, "A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET," 2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, pp. 330-332.
[16] B. Razavi, Design of Analog CMOS Integrated Circuits, 1st ed. McGraw-Hill, 2002.
[17] K. Obata, K. Matsukawa, T. Miki, Y. Tsukamoto and K. Sushihara, "A 97.99 dB SNDR, 2 kHz BW, 37.1 μW noise-shaping SAR ADC with dynamic element matching and modulation dither effect," 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016,pp. 1-2.
[18] Y. Shu, L. Kuo and T. Lo, "An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS,"in IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2928-2940, Dec. 2016.
[19] J. Liu, X. Wang, Z. Gao, M. Zhan, X. Tang and N. Sun, "A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping," 2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, pp. 158-160.
[20] C. Liu and M. Huang, "A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter," 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 466-467.
[21] C. Lillebrekke, C. Wulff and T. Ytterdal, "Bootstrapped switch in low-voltage digital 90nm CMOS technology," 2005 NORCHIP, 2005, pp. 234-236.
[22] Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, S.-P. U, R. P. Martins, and F. Maloberti, "A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS," in IEEE Journal of Solid-StateCircuits, vol. 45, no. 6, pp. 1111-1121, Jun. 2010.
[23] S. W. M. Chen, R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669–2680, Dec. 2006.
[24] H. Garvik, C. Wulff and T. Ytterdal, "An 11.0 bit ENOB, 9.8 fJ/conv.-step noise-shaping SAR ADC calibrated by least squares estimation," 2017 IEEE Custom Integrated CircuitsConference (CICC), 2017, pp. 1-4.
[25] S. Pavan, R. Schreier, and G. C. Temes, Understanding Delta-Sigma Data Converters, 2nd ed. Piscataway, NJ, USA: IEEE Press, 2017.
[26] J. M. de la Rosa, "Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol.58, no. 1, pp. 1-21, Jan. 2011.
[27] M. A. Ghanad, C. Dehollain and M. M. Green, "Noise analysis for time-domain circuits," IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp.149-152.
[28] S. Li, B. Qiao, M. Gandara, D. Z. Pan and N. Sun, "A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure," in IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3484-3496, Dec. 2018.

簡易檢索 / 詳目顯示

相關論文