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研究生: 王嗣裕
Szu-Yu Wang
論文名稱: 能帶隙工程矽-氧-氮-氧-矽快閃記憶體元件之可靠度與製程效應研究
Reliability and Processing Effects of Bandgap Engineered SONOS (BE-SONOS) Flash Memory Devices
指導教授: 龔正
Jeng Gong
口試委員:
學位類別: 博士
Doctor
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 英文
論文頁數: 106
中文關鍵詞: 矽-氧-氮-氧-矽 元件氧-氮-氧 穿隧介電層製程效應可靠度快閃記憶體
外文關鍵詞: Bandgap Engineering, SONOS, ONO Tunneling Dielectric, Processing Effect, Reliability, Flash Memory
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  • Charge-trapping memory devices are forecasted to be the solution for Flash memory beyond 40 nm node. SONOS device that introduced in late 1960’s is one type of charge-trapping memory devices in which charges are trapped in silicon nitride material. However, the conventional SONOS has a fundamental limitation that there is no suitable thickness for tunnel oxide to achieve good erase speed and data retention performance at the same time.
    Recently, a new charge-trapping Flash memory device named bandgap engineered SONOS (BE-SONOS) is proposed to overcome the fundamental limitation of SONOS. With the help of bandgap engineering in the very thin ONO tunneling barrier (typical of 13/20/25 Å for O1/N1/O2), the band-offset under high electric field can reduce the hole tunneling distance effectively because the O1 is almost the only effective tunneling barrier and thus a large hole current is allowed. On the other hand, at low electric field during retention, both electron de-trapping and hole direct tunneling are completely prohibited by the total barrier thickness (O1+N1+O2).
    In this thesis a more detailed understanding of BE-SONOS reliabilities is given including the device concept, processing effects on different dielectric layers, effect of charge-trapping layer engineering, and the capability of dielectric scaling. From the results in confidence, we believe BE-SONOS is so far the best choice of charge-trapping memory devices on the next-generation applications of non-volatile semiconductor memory (NVSM), especially for NAND Flash memory.


    電荷捕捉記憶體元件預期將成為快閃記憶體於40奈米以下世代產品的解決方案。於1960年代末期發明之矽-氧-氮-氧-矽(SONOS)元件就是其中一種型態的電荷捕捉記憶體元件。該種元件是將電荷儲存在氮化矽材料當中。然而,傳統的SONOS記憶體元件存在著一種應用上的限制,就是我們無法找到一個合適的穿隧氧化層厚度來同時達到優良的抹除速度以及資料保存能力。
    最近這幾年一種新的電荷捕捉快閃記憶體元件被提出具有克服傳統SONOS元件應用上限制的能力。該種記憶體元件稱作能帶隙工程矽-氧-氮-氧-矽(BE-SONOS)元件。在採用非常薄的氧-氮-氧穿隧阻障層(一般來說各層厚度約在13/20/25 埃)的情況下,高電場下的電荷穿隧距離會因為能帶隙消除效應而有效降低。此時幾乎僅存第一層超薄氧化層扮演有效之電荷穿隧障礙,因此大大提高了電洞穿隧電流。另一方面當電荷儲存狀態的低電場條件下,不論電子自儲存層中逸失或是電洞穿隧進入儲存層之能力皆會因為整個氧-氮-氧穿隧阻障層的阻擋而顯著降低。
    本論文將針對此新開發的BE-SONOS記憶體元件在基本元件概念、各介電層之製程效應、電荷捕捉層工程效應、以及介電層微縮能力在可靠度特性上之研究提供詳細的說明。從這些研究結果我們認為在次世代的非揮發性記憶體,特別是資料儲存式快閃記憶體(NAND Flash)的應用上,BE-SONOS是目前電荷捕捉記憶體元件當中的最佳解決方案。

    Chapter 1 Introduction 1 Chapter 2 Recent Progress of Charge-Trapping Memory Devices 6 2.1 Conventional SONOS Devices 6 2.1.1 Programming and Erasing Operations of SONOS Devices 7 2.1.2 Problem of Conventional SONOS Device 8 2.2 Charge-Trapping Flash Memory Devices for Scaling Solutions 9 2.2.1 NROM 9 2.2.2 TANOS 12 2.2.3 BE-SONOS 14 Chapter 3 Reliability and Processing Effects of BE-SONOS Memory Device 40 3.1 ONO Barrier Dependence 41 3.2 Top Dielectric Dependence 42 3.3 Trapping Material Dependence 45 Chapter 4 Extensive Study of Trapping-Layer Engineering of Charge-Trapping Memory Devices 58 4.1 Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method 59 4.1.1 Background of GSCS Transient Analysis Method 59 4.1.2 Theory Part of GSCS Transient Analysis Method 61 4.2 Sample Preparation and Process Description 63 4.3 Electron Capture Efficiency 64 4.4 Analysis of Vertical Charge Location in Various Charge-Trapping Layers 66 4.5 Reliability Evaluation by BE-SONOS Capacitors 68 Chapter 5 Capability of Dielectric Scaling of BE-SONOS Memory Device 82 5.1 Erase Performance 83 5.2 Gate Disturbance 83 5.3 P/E Cycling Endurance 85 5.4 Data Retention 85 Chapter 6 Conclusion 93 References 96 Publication 102

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