在現代的VLSI設計裡，晶片的複雜度大大的增加，而且導線(wires)及邏輯閘(gates)的數目大量的成長，甚至到千萬這麼多。在有限的晶片空間裡，達到預期延遲(delay)地繞線與擺放緩衝(buffer)變的越來越困難。例如，當已經在晶片上繞好的導線沒有盡量地避免壅塞的區域，一些將要被繞的導線很容易會有因為要多繞路而違反延遲的窘境。再者，導線在壅塞的區域可能會遭受到一些風險，例如鄰近導線的訊號干擾變強或是晶片製程上的失誤機率變大等。另一方面，擺放緩衝若沒有注意壅塞程度(congestion)而插在壅塞的區域，則後來較重要的導線若要插入緩衝在那區域減少延遲就會有可能發生困難。因此，在晶片上考慮壅塞程度變的越來越重要。分散壅塞程度可以幫助達到成功且完整地繞(routing)及擺排(placement)。
在這篇論文中，我們的貢獻是提供一個演算法去進一步改善一個給定緩衝樹(buffered tree)的壅塞程度，甚至改善延遲。隨著此演算法的緩衝樹分解觀念可以將一棵緩衝樹分解成一堆元件，我們可以很快找到這些元件的起點及一些起點週遭的替代點。我們可以使用幾個已經建好的元件表，透過這些替代點我們可以有許多重繞的路徑去找較好的緩衝樹延遲與壅塞程度。在我們的實驗中，我們將論文[4]中所產生的緩衝樹當作我們的測試目標。實驗結果顯示我們的演算法對這些測試目標的壅塞程度最高可以改進到43%以及延遲最高可以改進15.8%。

In modern VLSI designs, the complexity of a chip critically increases and the numbers of wires and gates enormously grow. It becomes difficult to route wires and place buffers to meet timing in limited space. For example, the nets which are ready to route are easy in awkward situations of timing violation due to detour, when the nets which are already routed do not avoid congested regions as many as possible. Moreover, interconnects in crowded regions may suffer some risks, like crosstalk, OPC etc. Therefore, considering congestion information turns into more and more important. Dispersing congestion can help to achieve successful and complete placement and routing.
In this thesis, our contribution is to give an algorithm to further improve congestion and even timing of a given buffered tree. By decomposing a buffered tree into several components and selecting alternative positions to move the drivers of these components, we can use pre-computed look-up tables to reroute the buffered tree such that the congestion and even timing can be improved. In our experiments, we used the buffered trees which are created by [4] to be the testcases. Experimental results show that our algorithm can improve the congestion up to 43% and timing 15.8%.

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[2] C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, A. Kahng, J. Lillis, B. Liu, S. Sapatnekar, A. Sullivan, and P. Villarubia, “Buffered Steiner Trees for Difficult Instances”, in Proc. Int. Symp. on Physical Design, 2001, pp. 4 – 9.

[3] J. Cong, and X. Yuan, “Routing Tree Construction under Fixed Buffer Locations”, in Proc. Design Automation Conf., 2000, pp. 379 – 384.

[4] S. Dechu, Zion C. Shen, and Chris C. N. Chu, “An Efficient Routing Tree Construction Algorithm with Buffer Insertion, Wire Sizing and Obstacle Considerations”, in Proc. Asia South Pacific Design Automation Conf., 2004, pp. 361-366.

[5] L.P.P.P. van Ginneken, “Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay”, in Proc. Int. Symp. on Circuits and Systems, 1990, pp. 865 - 868.

[6] M. Hrkic, and J. Lillis, “Buffer Tree Synthesis with Consideration of Temporal Locality, Sink Polarity Requirements, Solution Cost and Blockages”, in Proc. Int. Symp. on Physical Design, 2002, pp. 98 – 103.

[7] J. Hu, C. J. Alpert, S. T. Quay, and G. Gandham, “Buffer Insertion with Adaptive Blockage Avoidance”, in Proc. Int. Symp. on Physical Design, 2002, pp. 92 – 97.

[8] M. Lai, and D. F. Wong, “Maze Routing with Buffer Insertion and Wiresizing”, in Proc. Design Automation Conf., 2000, pp. 374 – 378.

[9] C. Y. Lee, “An Algorithm for Path Connection and Its Application”, IRE Trans. Electronic Computer, EC-10, 1961, pp. 346-365.

[10] C. N. Sze, J. Hu, and C. J. Alpert, “A Place and Route Aware Buffered Steiner Tree Construction”, in Proc. Asia South Pacific Design Automation Conf., 2004, pp. 355-360.

[11] X. Tang, R. Tian, H. Xiang, and D. F. Wong, “A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints”, in Proc. Int. Conf. on Computer Aided Design, 2001, pp. 49 – 56.

[12] H. Zhou, D. F. Wong, I. M. Liu, and A. Aziz, “Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations”, in Proc. Design Automation Conf., 1999, pp. 96 – 99.