應用在高速傳輸通訊操作在6.4GHz之全數位式鎖相迴路

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研究生：	張啟樺 CHANG, CHI-HUA
論文名稱：	應用在高速傳輸通訊操作在6.4GHz之全數位式鎖相迴路 A 6.4-GHz Bang-Bang PLL for High Speed Serial Data Communications
指導教授：	朱大舜 Chu, Ta-Shun
口試委員:	吳仁銘 Wu, Jen-Ming 王毓駒 Wang, Yu-Jiu
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2022
畢業學年度：	110
語文別：	中文
論文頁數：	65
中文關鍵詞：	鎖相迴路、全數位式鎖相迴路、數位控制振盪器
外文關鍵詞：	Phase-Locked Loop, All-Digital Phase-Locked Loop, Digital Controlled Oscillator
相關次數：	點閱：2 下載：0
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全數位式鎖相迴路相較於類比式與數位式鎖相迴路，透過大幅度的減少類比電路，進而降低了對電源和基板雜訊的敏感性，並且有著更好的雜訊容忍度。隨著先進製程的演進，數位電路容易地跟隨著製程一起縮小面積，同時，產品在重新設計上的時間也能減少，數位電路測試可以利用成熟的測試方法來完成。
本論文提出振盪頻率為6.4GHz應用在傳輸通訊上的全數位式鎖相迴路，其中相位頻率偵測器採用新型二元相位偵測器，降低電路延遲以增加穩定度。
數位濾波器之電路設計為了消除二元相位偵測器造成鎖定時間較長，電路中包含掃描鏈(Scan Chain)路徑，以加速電路鎖定。
數位控制振盪器提供6.3GHz到6.6GHz的可調範圍，本體採用電容電感式振盪器，透過切換式電容去改變電容大小來控制輸出頻率，最終，透過以上子電路建構出完整的全數位式鎖相迴路電路架構。
論文的開頭說明了本論文的動機，並對於常見的相迴路基本架構做了介紹，同時進行了比較，緊接著依序講解全數位式鎖相迴路非線性數學模型、設計電路的流程並進行內外部雜訊源的貢獻分析，本論文採用台積電65奈米製程技術加以實現，透過多組的模擬，幫助最佳化設計，此電路供應電壓為1.2伏特，整體系統總功耗功率為6.218mW。

Compared with Analog and Digital Phase-Locked Loop, All-Digital Phase-Locked Loop reduces the sensitivity of power supply and the substrate noise by greatly reducing Analog Circuits, which has better noise tolerance. With the evolution of advanced manufacturing processes, Digital Circuits can easily be reduced in area along with the manufacturing process, the time for product redesign can be reduced as well, Testing of Digital Circuits can be done by using mature testing methods.
This paper proposes an All-Digital Phase-Locked Loop with an oscillation frequency of 6.4GHz used in transmission and communication. The phase frequency detector adopts a new type of Sense-Amplifier-Based Flip-Flop , which reduces the circuit delay to increase the stability.
In order to eliminate the long locking time caused by the bang-bang phase detector, the circuit design of the digital loop filter includes a Scan Chain path to speed up the circuit locking.
The digitally controlled oscillator provides an tuning range from 6.3GHz to 6.6GHz. Using LC oscillator which output frequency is controlled by switch capacitor. Finally, the complete All-Digital Phase-Locked Loop circuit architecture is constructed through the above sub-circuits.
The motivation of this paper is explained at the beginning of the paper, and the basic architecture of common Phase-Locked Loop is introduced. The contribution of external noise sources is analyzed. This paper is implemented by the TSMC 65nm process.
Through multiple sets of simulations, these help to optimize the design and provide a conclusion . The supply voltage of the circuit is 1.2 volts, and the total power consumption is 6.218mW.

摘要    i
Abstract    ii
目錄    iii
圖目錄    v
表目錄    ix
第一章 緒論    1
1 研究動機    1
2 論文章節介紹    2
第二章 鎖相迴路架構與基本原理介紹    3
1 簡介    3
2 數位式鎖相迴路    3
2.1 相位頻率偵測器(Phase Frequency Detector，簡稱PFD)    4
2.2 電荷幫浦(Charge Pump，簡稱CP)    5
2.3 迴路濾波器(Loop Filter，簡稱LF)    7
2.4 壓控振盪器(Voltage Control Oscillator，簡稱VCO)    9
2.5 除頻器(Divider)    12
2.6 數位式鎖相迴路分析    13
2.7 數位式鎖相迴路相位雜訊分析    15
3 全數位式鎖相迴路    17
3.1 時間數位轉換器    18
3.2 二元相位偵測器    19
3.3 數位迴路濾波器    22
3.4 數位控制振盪器    23
3.5 全數位式鎖相迴路分析    24
第三章 全數位鎖相迴路系統分析    26
1 全數位鎖相迴路時域模擬    26
2 全數位鎖相迴路時域穩定度模擬    30
3 全數位鎖相迴路相位雜訊分析    33
第四章 6.4GHz全數位鎖相迴路設計與實現    38
1 Verilog-A 模型建立    38
1.1 二元相位偵測器行為模型    38
1.2 數位迴路濾波器振盪行為模型    39
1.3 數位控制振盪器行為模型    40
1.4 除頻器行為模型    40
1.5 全數位鎖相迴路行為模型    41
2 全數位鎖相迴路設計    43
2.1 二元相位偵測器電路設計    43
2.2 數位濾波器電路設計    47
2.3 數位控制振盪器電路設計    48
2.4 除頻器電路設計    53
第五章 模擬結果與佈局佈線    56
1 最佳相位雜訊模擬結果    56
2 各電路佈局佈線圖    59
2.1 數位控制振盪器佈局佈線圖    59
2.2 二元相位偵測器佈局佈線圖    60
2.3 數位控制振盪器佈局佈線圖    60
2.4 除頻器佈局佈線圖    61
3 模擬結果    62
第六章 結論    63
1 總結    63
參考文獻    64

                                

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