橫向式超接面閘流體過壓保護元件的設計與研究

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研究生：	周耕宇 Keng-Yu Chou
論文名稱：	橫向式超接面閘流體過壓保護元件的設計與研究 The Design and Research of Lateral Super-Junction Thyristor Surge Protective Device
指導教授：	龔正 Jeng Gong
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	中文
論文頁數：	98
中文關鍵詞：	矽控整流器、橫向式閘流體、閘流體過壓保護元件、超接面、埋藏層、崩潰電壓
外文關鍵詞：	SCR, Lateral Thyristor, TSPD, Super junction, Buried layer, Breakdown voltage
相關次數：	點閱：2 下載：0
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在現代深次微米尺寸的積體電路產品中，電晶體元件對突波和靜電放電變得非常敏感。矽控整流器（SCR）在突波放電的保護元件中，具有很好的突波放電防護能力，應用在晶片上也有一段很長的時間。
一般功率元件為了高電壓的應用，通常必須降低漂移區的摻雜濃度與增加其長度，相對的增加了導通電阻（Ron），傳統的閘流體過壓保護元件（TSPDs, Thyristor Surge Protective Devices）也免不了如此的設計，使得元件的額定電流受到限制。近幾年來，CoolMOSFET搭配超接面（Super-junction）結構，使其在相同崩潰電壓下導通電阻能比一般功率元件低很多。
本論文中，我們將傳統垂直式的閘流體改為橫向式結構，並依據超接面理論與閘流體做結合。使用三維模擬軟體進行元件的電性分析，研究結果顯示超接面使電場分佈較為平坦化，可有效提升元件的崩潰電壓。如果能加入深埋藏層的結構，有Double RESURF的效果能使崩潰電壓超過1000V以上。
根據上述，我們利用光罩和實際製程，嘗試設計出一個額定電壓為600V的橫向式超接面閘流體過壓保護元件（Lateral Super-junction TSPD）。

摘要....................................................Ⅰ
誌謝....................................................Ⅲ
目錄....................................................Ⅳ
第一章 緒論.............................................1
  1.1簡介...............................................1
  1.2論文摘要...........................................3
第二章 閘流體保護元件的發展與回顧.......................4
  2.1閘流體保護元件的種類...............................5
     2.1.1相位控制閘流體................................6
     2.1.2反向器閘流體..................................7
     2.1.3非對稱閘流體..................................8
     2.1.4反向導通閘流體................................8
     2.1.5閘極關斷閘流體................................9
     2.1.6光觸發閘流體.................................10
  2.2閘流體保護元件的規格..............................11
     2.2.1電性參數.....................................11
     2.2.2 溫度參數....................................13
     2.2.3閘極關斷閘流體參數...........................13
第三章 閘流體過壓保護元件的設計........................26
  3.1閘流體基本原理....................................26
     3.1.1基本結構.....................................26
     3.1.2陰極短路.....................................29
     3.1.3垂直式閘流體結構.............................29
  3.2超接面基本原理....................................30
     3.2.1超接面概觀...................................30
     3.2.2崩潰電壓與導通電阻...........................30
     3.2.3電荷平衡.....................................33
  3.3超接面閘流體的設計................................33
     3.3.1 崩潰電壓（Vbr）之設計.......................34
     3.3.2 維持電壓（VH）與維持電流（IH）之設計........35
第四章 元件製作與模擬..................................43
  4.1橫向式超接面閘流體之製作..........................43
     4.1.1光罩設計與規劃 ..............................43
     4.1.2製造步驟.....................................45
  4.2橫向式超接面閘流體之模擬 .........................47
     4.2.1橫向式閘流體之二維模擬 ......................47
          4.2.1.1調整LOCOS厚度之模擬...................49
          4.2.1.2調整氧化層沈積厚度之模擬..............49
          4.2.1.3調整場板長度之模擬....................49
          4.2.1.4調整P-base之模擬......................49
          4.2.1.5調整漂移區長度之模擬..................50
     4.2.2橫向式超接面閘流體之三維模擬.................50
          4.2.2.1調整超接面深度之模擬..................52
          4.2.2.2調整超接面寬度之模擬..................52
          4.2.2.3調整超接面長度之模擬..................52
  4.3量測結果 .........................................54
第五章 結論............................................92
參考文獻 ..............................................94

                                

[1] J. L. Moll, M. Tanenbaum, J. M. Goldey, and N. Holonyak, Jr., “p-n-p-n transistor switches, ” Proc. IRE, vol.44, p. 1174, 1956.

[2] R. W. Aldrich and N. Holonyak, Jr., “Multi-terminal p-n-p-n switches,” Proc. IRE, vol. 46, pp.1236-1239, 1958.

[3] J. M. Goldey, I. M. Makintosh, and I. M. Ross, “Turn-off gain in p-n-p-n triodes,” Solid-State Electron., vol.3, p.119, 1961.

[4] F. E. Gentry, R. T. Scace, and J. K. Flowers, “Bidirectional triode p-n-p-n switches,” Proc. IEEE, vol.53, pp.355-369,19.

[5] E. K. Howell, “The light actuated SCR,” Appl. Note 200.34, General Electric Co., Schenectady, NY, 1965.

[6] F. E. Gentry and J. Moyson, “The amplifying gate thristor,” presented at IEEE Int. Electroc Device Meet., Washington, DC, 1968.

[7] R. A. Kokosa and B. R. Tuft, “A high-voltage, high temperature reverse conducting thyristor,” IEEE Trans. Electron Devices, vol. ED-17, no.9, pp.667-672, 1970.

[8] D. E. Houston, S. Krishna, D. Piccone, R. J. Finke, and Y. S. Sun, “Field-controlled thyristor（FCT）- A new electronic component,” presented at IEEE Int. Electron Device Meet., Wachington, DC, 1975.

[9] V. A. K. Temple and R. P. Love, “A 600V MOSFET with near ideal on-resistance,” in IEDM Tech. Dig., pp.664-666, 1978.

[10] J. D. Plummer and B. W. Scharf, “Insulated gate planar thyristors,” IEEE Trans. Electron Devices, vol. ED-27, pp. 380-394, 1980.

[11] A, Pshaenich, “The MOS-SCR, A new thyristor technology,” Motorola Engineering Bull. ED-103, 1982.

[12] B. J. Baliga, M. S. Adler, P. V. Gray, R. P. Love, and N. Zommer, “The insulated gate rectifier（IGR）：A new power switching device,” in IEDM Tech. Dig., pp.264-267, 1982.

[13] M. Otsuka, “The forward characteristics of thyristors”, Proc. IEEE, vol.55, no.8, Aug.1967.

[14] H. F. Storm and J. G. St. Clair, “An involute gate-emitter configuration for thyristors, ” Trans. IEEE Japan, 1973.

[15] A. A. Jaecklin, “Structure of an efficient high power reverse conducting thyristor,” presented at IEEE Power Division Colloquium, London, England, Dec.1, 1978.

[16] P. S. Raderecht, “The development of a gate-assisted turn-off thyristor for use in high frequency applications,” Int. J. Electron., vol.36, pp.399-416, 1974
[17] E. S. Schlegel, “Gate-assisted turn-of thyristors,” IEEE Trans. Electron Devices, vol. ED-23, pp.888-892, 1976.

[18] J.Shimiza et al. “High-voltage high-power gate-assisted turn-off thyristor for high-frequency use,” IEEE Trans. Electron Devices, vol. ED-23, no.8, pp.883-887, 1976.

[19] V. A. K Temple and A. P. Ferro, “High power dual gate light-triggered thyristors,” IEEE Trans. Electron Devices, vol. ED-23, p. 893, 1976.

[20] E. Schlegel and D. Page, “A high power light activated thyristors,” in IEDM Tech.Dig., p.483, 1976.

[21] IEEE Standard Test Specification for Thyristor Diode Surge Protective Devices, IEEE Std C62.37-1996.

[22] P.D.Taylor, Thyristor Design and Realization,Wiley,New York,1993.

[23] J.J. Ebers, “Four-Terminal p-n-p-n Transistor”Proc.IEEE,40,1361(1952)

[24] D.A.Neamen“Semiconductor Physics AND DEVICES Basic Principle” 3rd ,2003. pp. 688-689.

[25] B.J. Baliga, “Power Semiconductor Devices”,PWS. Publishing company, 1995. pp. 265-266.

[26] T.Fujihira, “Theory of semiconductor superjunction devices”, Jpn. J. Appl. Phys., Vol. 36, pp.6254-6262, 1997

[27] G. Dobey, M. Marz, J.P. Stengl, H. Strack, J. Tihanyi and H. Weber, “A new generation of high voltage MOSFETs breaks the limit line of sili- con”, IEDM Tech Digest, pp.683-685, 1998.

[28] L. Lorenz, G. Dobey, A. Knapp and M. Marz, “COOLMOSTM-a new
milestone in high voltage power MOS”, ISPSD’ 1999, pp.3-10, 1999.

[29] D.J.Coe,”High Voltage Semiconductor Superjunction device”, U.S. Patent4754310, June 28, 1998.

[30] X.B. Chen, P.A. Mawby, K. Board, C.A.T. Salama, “Theory of a novel
voltage-sustaining layer for power devices”, Microelectronics journal
29 (1998) 1005-1011.

[31] T.Fujihira, Y. Onishi, S.Iwamoto,T. Sato, “24 mΩ-cm-2 680V Silicon
Superjunction MOSFET” ,Power Semiconductor Devices and ICs, 2002. Proceedings of the 14th International Symposium, pp241 – 244, 2002

[32] Min Liu, C. A. T. Salama, P. Schvan and M. King, “A fully resurfed, BiCMOS- compatible , high voltage MOS transistor”, ISPSD '96, pp. 143-146.

[33] ATHENA, 2D Process Simulation Software, Version-5.15.3.R, SILVACO International.

[34] DevEdit3D, Device Structure Editor, Version-2.8.5.R, SILVACO International.

[35] ATLAS, Device Simulation Software, Version-5.13.6.C, SILVACO International.

[36] Fu-Hsiung Yang, “The Design of 600V Vertical Super-Junction TSPDs”, NTHU-2006.6.

[37] Chung-Yo Hung, “The Design of 600V Lateral Super-Junction Thyristor Surge Protective Device”, NTHU-2007.6.

[38] M. Imam, Z. Hossain, M. Quddus, J. Adams, C. Hoggatt, T. Ishiquro, R.Nair, “Design and optimization of double-RESURF high-voltage lateral devices for a manufacturable process”, Electron Devices, IEEE Transactions on, vol. 50, pp.1697-1700, July 2003

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