憶阻器(Memristor)因同時具有非揮發性存儲與邏輯計算的能力，被視為有潛力的記憶體內運算平台的候選者。近年來，已經有眾多不同風格且基於憶阻器交錯陣列的通用運算平台被提出。然而憶阻器自身的元件特性與外部讀取電路的限制，可能會導致邏輯合成時額外的延遲與面積開銷。因此在本文中，我們提出了一種基於單一憶阻器元件的多週期的邏輯運算的邏輯合成方法，可在這些限制下，在面積受限的憶阻器交錯式陣列中進行任意布爾邏輯函式的合成。 我們在ISCAS'85的測試電路的實驗結果表明，我們的方法可以有效地減少單行讀出約束的開銷。 此外，我們的方法能夠在行和列方向上進行平行的運算。而我們在更大的EPFL測試電路上進行的的實驗結果，表明我們的方法的有效性與擴展性。

Memristors are considered as promising candidates for Computation-In-Memory due to their non-volatile storage and computing capabilities. In recent years, a growing number of general-purpose computing platforms based on different design styles at the memristor crossbar arrays have been proposed. In this paper, we present a comprehensive synthesis approach for performing arbitrary Boolean logic operations in area-constrained crossbar arrays. The approach exploits multicycle logic operations to deal with the delay and area constraints.

The experimental results on ISCAS'85 benchmarks show that our approach can effectively reduce the overhead of one-row readout constraint, which needs many cycles to move data. Our approach is also capable of performing operations parallel in both row and column directions. The experimental results at larger EPFL benchmarks show that our approach is robust and scalable.

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