隨著超大型積體電路製程不斷縮小化、操作電壓不斷下降，對於數位電路而言有著功率消耗下降的優點。然而對於類比電路而言卻不盡然，不僅在維持相同動態範圍（Dynamic Range）下，功率消耗隨操作電壓下降而上升，且電晶體尺寸縮小化直接造成其輸出阻抗下降，如何維持相同的電壓增益便成為一個需要被解決的課題。短通道電晶體與長通道電晶體特性並不全然相同，因此許多在以往設計中所遵守的設計準則需要被適度的修正以因應短通道電晶體的工作特性。本文針對以往設計放大級時採用負電導耦合對必須遵守的迴授電導與負載電導之電導比小於0.9的準則提出修正，並且以此修正方式設計一適用於低電壓（1.5V）8位元50MS/s類比數位轉換器使用0.35um CMOS 1P4M Technology之全差動放大器。本文修正方式在完全多不耗費晶片面積與功率消耗下，較以往設計準則增加約20dB低頻開迴路增益且不影響其單一增益頻率。但利用此方式設計，對於低頻開迴路增益的有效控制有一定程度的影響所以需多增加安全範圍以利整體效能達到預期。同時本文以此放大器設計一低電壓（1.5V）8位元50MS/s脈管式類比數位轉換器。本文採每單級1.5位元，共8級。為避免功率消耗增加過大，在每單級1.5位元的架構上做改善，可節省2個比較器與2個鎖相器的功率消耗。如此由Hspice模擬並由Matlab做DFT分析結果可得本文設計在輸入頻率為20MHz且取樣頻率為50MHz的條件下，有效位元數（ENOB）大於7位元。

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