COMS元件在具有低耗能、發熱少且省電的優點，在未來應用在CMOS元件技術中等效氧化層厚度(EOT)被要求縮小到1.0 nm以下。因此使用High-k材料來縮小等效氧化層厚度並且降低漏電流，在High-k材料跟基材之間的介面層(Interfacial Layer)便扮演相當重要的角色。鍺相較於矽而言，電子的遷移率可提升兩倍、電洞的遷移率可以提升至四倍，故對於通道電流傳輸可以大大改善。但是由於GeOx(Ge sub-oxide)不耐高溫，在400℃下發生揮發，將會造成元件的電特性惡化，所以採用水氣電漿(H2O Plasma)方式來成長出高Ge4+含量的GeO2介面層。本論文的研究以ALD (Atomic Layer Deposition System)的水氣電漿做為沉積介面層的主要製程機台，以得到高品質的介面層GeO2為實驗主軸。
第一部分，改變每一次水氣電漿作用沉積後的等待時間，我們稱之為脫附時間(desorption time)，由於製程溫度固定在370℃，每次沉積的介面層分子中不穩定的GeOx (Ge sub-oxide)將會在這個脫附時間離開介面層，留下GeO2在介面層中，從XPS的物性分析中可以明顯看出脫附時間越長，介面中所含的Ge4+就越多。成功微縮元件的等效氧化層厚度(EOT)，達到3.95 Å，漏電Jg 約在100 A/μm2左右，超越目前最新文獻的7 Å。
第二部分為探討水氣電漿中氫氧根自由基含量對GeO2氧化層的影響，改變每次沉積週期中水氣的注入量，使電漿中氫氧根自由基的含量提高，提升和Ge的鍵結機會。從實驗結果可以看到，我們的元件表現並非和水氣注入量成正比，水氣注入量高，仍必須給予元件足夠的脫附時間才能夠使得沉積上去的GeOx擁有足夠的時間可以從介面脫附，而得到較佳的介面層。因此在這部分我們得到以水氣注入時間0.24秒的元件，其等效氧化層厚度(EOT)最小，約為3.1 Å。此章元件的XPS所看到的Ge4+含量差異不大，約在1~2%之間。
第三部分我們增加水氣電漿沉積週期以及水氣電漿作用在基材上的時間。從實驗結果可以發現元件介面層的厚度跟沉積週期並沒有成正比關係，沉積週期越長，厚度越不易增厚。在元件可靠度表現進步很多，從前兩部分的結果顯示Frequency Dispersion皆落在0.8 V到1 V之間，增加沉積週期的元件Frequency Dispersion被大大改善；平帶電壓位移量和Stress Induced Leakage Current (SILC)也有有極佳的表現與前兩部分相比也有優異的表現，我們推測是由於Ge-O鍵結的穩定，所以介面層中的缺陷明顯減少，電洞在介面層被缺陷困住的量減少，因而在可靠度上有優異的表現。從XPS上也得到超越目前文獻最高的介面層其Ge4+含量88%。除了展現純鍺基板電容的超薄等效氧化層厚度外，相當榮幸能夠在本論文的實驗中有效提升純鍺基板PMOS電容的可靠度。

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