在晶片設計上，主要包含了三個程序：硬體描述設計，實體設計和下線。在第一個階段中，主要利用硬體描述語言來設計所需要的電路。在第二個階段中，主要達成設計的收斂，裡面又分成很多細部的程序。在完成這兩個階段後，才能實際的下線得到所要的產品。一旦晶片設計者要重新修改晶片的功能，往往需要重跑整個流程，這消耗了成本和時間。
工程變化順序(Engineering change order)是一個應用在實體設計程序的技術。 在傳統的工程變化程序中，主要是利用多餘的邏輯閘(spare cells)均勻的散佈在晶片核心的區域。相較於重複地跑整個設計流程，當工程師需要對晶片的功能進行修改或希望達到時序上的收斂，可以利用這些多餘的邏輯閘來達成所要的目的。因為只需要對少數的金屬層進行修改的動作，能夠有效的減少成本和時間。
隨著製程的進步，供應的電壓逐年下降。這使得供應電壓變異的問題(supply voltage variation)變的更嚴重。同時也嚴重影響雜訊的辨別和晶片的速度。去耦電容(Decoupling capacitor)是一個有效的方法。在使用方法上，一般當晶片上有多餘的空間，就會放入所謂的去耦電容。藉由它的功能，可以有效的減少供應電壓的變異。
如上述所述，多餘的邏輯閘和去耦電容都需要佔去晶片上的面積。為了同時滿足上述的需求，我們設計了一種新的可重構元件(reconfigurable cell)。當工程師不需要對晶片的功能進行修改，這種元件就如同所謂的去耦電容，可以有效減少供應電壓的變異；而當工程師需要對晶片的功能進行修改，也可以利用這種元件，去達到所要的目摽。同時，為了有效的進行功能上的修改，我們設計了一套演算法，可以盡量不影響供應電壓的情況下，又能達到所謂的時序收斂。由實驗結果得知，使用我們的方法，可以減少20%的供應電壓變異量和56%的漏電流，同時也能夠有效地達到時序上的收斂。

Unused spare cells occur inevitably in traditional ECO design flow.It results in inefficient area usage, more leakage, more IR drop impacts and fixed locations of spare cell. To tackle these problems, a reconfigurable cell is proposed which served the dual purposes of decoupling capacitance and spare cell in this thesis. Before
Engineering Change Order (ECO) is applied, these cells are
pre-placed as decoupling capacitors. When ECO is applied, these cells are configured as spare cells. Moreover, based on our reconfigurable cell design, we proposed an algorithm to demonstrate the efficiency of our configurable cell for timing closure and IR drop minimization simultaneously. Compared with traditional ECO flow, our reconfigurable ECO flow shows 20% IR drop reduction and 56% reduction in leakage of spare cells with 10% spare area. In addition, there are less unsolved ECO timing paths left afterapplying our ECO timing optimization algorithm.

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