隨著製程進入奈米世代，積體電路中的高耗電(power consumption)與電路可靠度(circuit reliability)成為二個重大挑戰。在高耗電的挑戰中，有二個值得注意的問題，其一是漏電流(leakage current)問題，其次是最大電流(peak current)問題。過大的漏電流不僅會縮短電池使用壽命同時也可能導致過熱使得電路損壞。而為了使得電路能在最大電流過大的情況下仍能正常運作，電路設計者必須增加電源接腳及重新設計電源供給網路(power supply network)以避免電子轉移(electromigration)問題。而在電路可靠度的挑戰中，也有二個值得注意的問題，首先是製程變異(process variations)問題，再者是電源端雜訊(dynamic power noises)問題。在製程變異的情況下，同一片晶圓(wafer)上的部分電路會較慢。若是較慢的電路過多，會導致良率下降。而在電源端雜訊過大的情況下，會降低電路的效能或導致功能異常。由於單一的技術無法克服上述的所有問題，因此，在此論文中，我們對於三個重要的電路組件: 時鐘樹(clock tree)、電源供給網路和邏輯閘(functional gates)提出不同的技術以解決上述問題。
首先，對於時鐘樹，我們提出極性分配技術(polarity assignment technique)以解決最大電流及電源/接地端雜訊問題並同時控制時鐘樹上的時序差異(clock skew)。在之前的研究中，已有研究人員提出極性分配法以減少最大電流與電源/接地端雜訊問題。但在之前的研究中，雖然極性分配法可有效減小最大電流與電源/接地端雜訊卻增加時鐘樹上的時序差異。因此，我們提出一個新的極性分配技術可減少最大電流與電源/接地端雜訊並同時控制時鐘樹上的時序差異。
再者，對於電源供給網路，我們提出一個新的去耦合電容分配法(decoupling capacitor allocation)以降低電源端雜訊。為了在佈局(placement)前就能預知哪些邏輯閘有較高的機會遭受較大的電源端雜訊，我們提出一個同時考慮邏輯閘開關時間與位置的預估方法。對於有較高機會遭受較大電源端雜訊的邏輯閘，會在佈局前將它與去耦合電容結合後，再由佈局工具(placement tool)佈局。然而，由於在佈局後，部分電路區塊仍可能遭受較大的電源端雜訊。因此，在佈局後，我們提出一個將邏輯閘從遭受較大電源端雜訊的區塊移出，再於空出的空間加上去耦合電容的方法取代消極地只在現有空白空間(free space)放置去耦合電容的方法。
最後，對於邏輯閘，我們提出一個新的電路分割方法，對於每一個電路分割區塊，利用基底偏壓(body biasing)技術以減小漏電流及製程變異的影響。基底偏壓技術可分為二種，第一種是反向基底偏壓(reverse body biasing)技術會使邏輯閘的漏電流減少但增加邏輯閘的延遲(delay)，第二種是正向基底偏壓(forward body biasing)技術會使邏輯閘的漏電流增加但減少邏輯閘的延遲。在此論文中，我們會將電路做分割，對於每一個電路分割區塊提供適合的反向基底偏壓或正向基底偏壓技術以減少漏電流並使得電路能符合速度要求(timing constraint)。

[1] J. P. Uyemura, ”Introduction to VLSI circuits and systems,” JOHN WILEY & SONS, INC.
[2] L. H. Chen, M. Marek-Sadowska, and F. Brewer, ”Buffer delay change in the presence of power and ground noise,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 461-473, Jun. 2003.
[3] S. S. Sapatnekar and H. Su, ”Analysis and optimization of power grids,” IEEE Design and Test Computers, vol. 20, no. 3, pp. 7-15, May-Jun. 2003.
[4] Y.-T. Nieh, S.-H. Huang, and S.-Y. Hsu, ”Minimizing peak current via opposite phase clock tree,” ACM/IEEE Design Automation Conference (DAC), pp. 182-185, Jun. 2005.
[5] R. Samanta, G. Venkataraman, and J. Hu, ”Clock buffer polarity assignment for power noise reduction,” ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 558-562, Nov. 2006.
[6] R.-S. Tsay, ”Exact zero skew,” ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 336-339, Nov. 1991.
[7] J. P. Fishburn, ”Clock skew optimization,”IEEE Transactions on Computers, vol. 39, no. 7, pp. 945-951, Jul. 1990.
[8] G. Venkataraman, N. Jayakumar, J. Hu, P. Li, S. Khatri, A. Rajaram, P. McGuinness, and C. Alpert, ”Practical techniques to reduce skew and its variations in buffered clock networks,” ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 591-595, Nov. 2005.
[9] M. R. Guthaus, D. Sylvester, and R. B. Brown, ”Clock buffer and wire sizing using sequential programming,”ACM/IEEE Design Automation Conference (DAC), pp. 1041-1046, Jul. 2006.
[10] Synopsys, ”http://www.synopsys.com/”.
[11] Cadence, ”http://www.cadence.com/”.
[12] C.-Y. Yeh and M. Marek-Sadowska, ”Timing-aware power noise reduction in layout,” ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 627-634, Nov. 2005.
[13] S. Pant and D. Blaauw, ”Timing-aware decoupling capacitance allocation in power distribution networks,” ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 757-762, Jan. 2007.
[14] S. Pant, D. Blaauw, V. Zolotov, S. Sundareswaran, and R. Panda, ”Vectorless analysis of supply noise induced delay variation,” ACM/IEEE International Conference
on Computer-Aided Design (ICCAD), pp. 184-191, Nov. 2003.
[15] H. Su, S. S. Sapatnekar, and S. R. Nassif, ”Optimal decoupling capacitor sizing and placement for standard-cell layout designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, issue 4, pp. 428-436, Apr. 2003.
[16] Y. Zhong and M. D. F.Wong, ”Fast algorithms for IR drop analysis in large power grid,” ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 351-357, Nov. 2005.
[17] M. Popovich, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, ”Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs,” ACM/IEEE
International Conference on Computer-Aided Design (ICCAD), pp. 811-816, Nov. 2007.
[18] A.-C. Hsieh, T.-T. Lin, T.-W. Chang, and T. Hwang, ”A functionality directed clustering technique for low power MTCMOS design - computation of simultaneously discharging current,” ACM Transactions on Design Automation of Electronic Systems, vol. 12, issue 3, Aug. 2007.
[19] H. Kriplani, F. N. Najm, and I. N. Hajj, ”Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: algorithms, signal correlations, and their resolution,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, issue 8, pp. 998-1012, Aug. 1995.
[20] L. T. Pillage, R. A. Rohrer, and C. Visweswariah, ”Electronic circuit and system simulaton methods,” McGraw-Hill.
[21] B. Hu and M. Marek-Sadowska, ”Wire length prediction based clustering and its application in placement,” ACM/IEEE Design Automatin Conference (DAC), pp. 800-805, Jun. 2003.
[22] M. Pan, N. Viswanathan, and C. Chu, ”An efficient and effective detailed placement algorithm,” ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 48-55, Nov. 2005.
[23] Y.-M. Kuo, Y.-T. Chang, S.-C. Chang, and M. Marek-Sadowska, ”Engineering change using spare cells with constant insertion,” ACM/IEEE International Conference
on Computer-Aided Design (ICCAD), pp. 544-547, Nov. 2007.
[24] D. K. Chen and J. A. Babcock, ”Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing,” J. Applied Physics,
vol. 94, no. 1, pp. 1-18, Jul. 2003.
[25] S. M. Martin, K. Flautner, T. Mudge, and D. Blaauw, ”Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads,” ACM/IEEE International Conference on Computer-Aided Desing (ICCAD), pp. 721-725, Nov. 2002.
[26] C. Neau and K. Roy, ”Optimal body bias selection for leakage improvement and process compensation over different technology generations,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 116-121,
Aug. 2003.
[27] N. Jayakumar, S. Dhar, and S. P Khatri, ”A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents,” ACM/IEEE Design Automation Conference (DAC), pp. 43-46, Aug. 2005.
[28] V. Khandelwal and A. Srivastava, ”Active mode leakage reduction using finegrained forward body biasing strategy,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 116-121, Aug. 2004.
[29] J. Tschanz, N. S. Kim, S. Dighe, J. Howard, G. Ruhl, S. Vangal, S. Narendra, Y. Hoskote, H. Wilson, C. Lam, M. Shuman, C. Tokunaga, D. Somasekhar, S. Tang, D. Finan, T. Karnik, N. Borkar, N. Kurd, and V. De, ”Adaptive frequency
and biasing techniques for tolerance to dynamic temperature-voltage variations and aging,” IEEE International Solid State Circuits Conference (ISSCC), pp. 292-293, Feb. 2007.
[30] G. Gammie, A. Wang, M. Chau, S. Gururajarao, R. Pitts, F. Jumel, S. Engel, P. Royannez, R. Lagerquist, H. Mair, J. Vaccani, G. Baldwin, K. Heragu, R. Mandal, M. Clinton, D. Arden, and U. Ko, ”A 45nm 3.5G baseband-and-multimedia application processor using adaptive body-bias and ultra-low-power techniques,” IEEE International Solid State Circuits Conference (ISSCC), pp. 258-259, Feb. 2008.
[31] S.-C. Chang, C.-T. Hsieh, and K.-C. Wu, ”Re-synthesis for delay variation tolerance,” ACM/IEEE Design Automation Conference (DAC), pp. 814-819, Jun. 2004.
[32] K. R. Heloue and F. N. Najm, ”Parameterized timing analysis with general delay models and arbitrary variation sources,” ACM/IEEE Design Automation Conference (DAC), pp. 403-408, Jun. 2008.
[33] K. R. Heloue, S. Onaissi, and F. N. Najm, ”Efficient block-based parameterized timing analysis covering all potentially cricital paths,” ACM/IEEE International
Conference on Computer-Aided Desing (ICCAD), pp. 173-180, Nov. 2008.
[34] K. Yang, K.-T. Cheng, L.-C. Wang, and J.-J. Liou, ”UCSB statistical timing simulator - DSIM.”
[35] BPTM. http://www-device.eecs.berkeley.edu/˜ptm.
[36] C. Chen, X. Yang, and M. Sarrafzadeh, ”Potential slack: An effective metric of combinational circuit performance,” ACM/IEEE International Conference on
Computer-Aided Desing (ICCAD), pp. 198-201, Nov. 2000.
[37] S. H. Kulkarni, D. Sylvester, and D. Blaauw, ”A statistical framework for postsilicon tuning through body bias clustering,” ACM/IEEE International Conference
on Computer-Aided Desing (ICCAD), pp. 39-46, Nov. 2006.
[38] S. H. Kulkarni, D. Sylvester, and D. Blaauw, ”Design-time optimization of postsilicon tuned circuits using adaptive body bias,” IEEE Transactions on Computer-
Aided Design of Integrated Circuits and Systems, vol. 27, no. 3, pp. 481-494, Mar. 2008.
[39] A. Keshavarzi, S. Narendra, B. Bloechel, S. Borkar, and V. De, ”Forward body bias for microprocessors in 130nm technology generation and beyond,” IEEE Symposium
on VLSI Circuits Digest of Technical Papers, pp. 312-315, Jun. 2002.
[40] Y.-F. Tsai, N. Vijaykrishnan, Y. Xie, and M. J. Irwin, ”Influence of leakage reduction techniques on delay/leakage uncertainty,” IEEE International Conference
on VLSI Design, pp. 374-379, Jan. 2005.
[41] C. S. Amin, N. Menezes, K. Killpack, F. Dartu, U. Choudhury, N. Hakim, and Y. I. Ismail, ”Statistical static timing analysis: How simple can we get?,” ACM/IEEE
Design Automation Conference (DAC), pp. 652-657, Jun. 2005.
[42] F.Wang, X.Wu and Y. Xie, ”Variability-driven module selection with joint design time optimization and post-silicon tuning,” ACM/IEEE Asia and South Pacific
Design Automation Conference (ASPDAC), pp. 2-9, Jan. 2008.
[43] C. Zhuo, D. Blaauw, and D. Sylvester, ”Variation-aware gate sizing and clustering for post-silicon optimization circuits,” ACM/IEEE International Symposium on
Low Power Electronics and Design (ISLPED), pp. 105-110, Aug. 2008.